JPH03171760A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03171760A JPH03171760A JP30908589A JP30908589A JPH03171760A JP H03171760 A JPH03171760 A JP H03171760A JP 30908589 A JP30908589 A JP 30908589A JP 30908589 A JP30908589 A JP 30908589A JP H03171760 A JPH03171760 A JP H03171760A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- connection hole
- semiconductor element
- surface connection
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 17
- 238000007639 printing Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000004593 Epoxy Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体素子搭載用回路基板を備えた半導体装
置の構造及びその製造方法に関するものである．
（従来の技術）
従来、半導体装置（半導体集積回路）で、特にＩＣカー
ド等に使用されるものは、パッケージの厚さが０．５ｍ
〜１．０ｍ程度の薄型であり、厚さ精度の厳しいパッケ
ージ構造が要求される．従来のかかる薄型のパ・冫ケー
ジ構造を持つ半導体装置としては、例えば、特開昭５５
− ５６６４７号に記載されるものがある．
これは、ガラスエボキシ等からなるＰＣＢ （印刷配線
基板：プリンテッド・サーキット・ボード）上に半導体
集積回路等の半導体素子を直接搭載し、この半導体素子
とＰＣＢ上の金属配線とをワイヤで接続した後、エボキ
シ樹脂などで封止するＣＯＢ（チップ・オン・ボード）
である．
このようなＣＯＢのバッケージの構造図を第２図及び第
３図に示す．
第２図はそのパッケージの部分平面図、第３図はそのパ
ッケージの断面図である．つまり、ガラスエポキシから
なる半導体素子搭載用回路基板を有する半導体装置の構
成が示されている．これらの図において、ｌはガラスエ
ポキシ基板、２は金属配線パターン、３は外部接続用端
子、４は葛面接続孔（バイヤスルーホール）、５は半導
体素子封止樹脂、６はパターン保護のソルダレジスト（
ＳＲ）、７は半導体素子、８は接続ワイヤである．
これらの図に示すように、裏面接続孔４は従来、第２図
に示すように、半導体素子封止樹脂５の封止領域外に設
けられている．これは、封止領域内に裏面接続孔４を設
けると、封止樹脂５が裏面接続孔４内に入り、裏面に流
れ出るためである．ここで、封止樹脂５の流出を防ぐた
めに、裏面接続孔４にソルダレジスト６を塗布しても、
第４図に示すように、やはり裏面接続孔４にソルダレジ
スト６が入り込んでしまい、完全に孔を塞ぐことはでき
なかった．第４図において、ｌＯはガラスエポキシ基板
、１ｌは化学銅及び電気銅メッキ、ｌ２はＮｉ−Ａｕメ
ッキ、１３はソルダレジストである．（発明が解決しよ
うとする！Ｉ！ｌ！）しかしながら、上記した従来の半
導体回路基板を有する半導体装置の構造では、半導体素
子封止樹脂の封止領域内に裏面接続孔を設けると、封止
樹脂が裏面側に流れ出すため、設計上、封止樹脂の封止
領域内には裏面接続孔は設けることができないといった
制約があった。ところが、半導体素子の高集積化により
、素子サイズは大きくなる一方、逆にパノケージ形状は
小型化する傾向にあるため、この設計上の制約は大きな
障害になっていた。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor device equipped with a circuit board for mounting a semiconductor element, and a method for manufacturing the same. (Prior Art) Conventionally, semiconductor devices (semiconductor integrated circuits), especially those used in IC cards, etc., have packages with a thickness of 0.5 m.
It is thin, about ~1.0m, and requires a package structure with strict thickness accuracy. As a conventional semiconductor device having such a thin package structure, for example, Japanese Patent Laid-Open No. 55
- There is something described in No. 56647. This is a system in which semiconductor elements such as semiconductor integrated circuits are directly mounted on a printed circuit board (PCB) made of glass epoxy, etc., and the semiconductor elements and metal wiring on the PCB are connected with wires. After that, COB (chip on board) is sealed with epoxy resin etc.
It is. Figures 2 and 3 show structural diagrams of such COB packages. Figure 2 is a partial plan view of the package, and Figure 3 is a sectional view of the package. In other words, the structure of a semiconductor device having a circuit board for mounting a semiconductor element made of glass epoxy is shown. In these figures, l is a glass epoxy board, 2 is a metal wiring pattern, 3 is an external connection terminal, 4 is a via hole, 5 is a semiconductor element sealing resin, and 6 is a solder for pattern protection. Resist (
SR), 7 is a semiconductor element, and 8 is a connection wire. As shown in these figures, the back surface connection hole 4 has conventionally been provided outside the sealing area of the semiconductor element sealing resin 5, as shown in FIG. This is because when the back surface connection hole 4 is provided in the sealing area, the sealing resin 5 enters the back surface connection hole 4 and flows out to the back surface. Here, in order to prevent the sealing resin 5 from flowing out, even if the solder resist 6 is applied to the back surface connection hole 4,
As shown in FIG. 4, the solder resist 6 entered the back connection hole 4, and the hole could not be completely closed. In FIG. 4, IO is a glass epoxy substrate, 1l is chemical copper and electrolytic copper plating, 12 is Ni-Au plating, and 13 is solder resist. (This is what the invention is trying to solve! I!l!) However, in the structure of a semiconductor device having the conventional semiconductor circuit board described above, if a back side connection hole is provided in the sealing area of the semiconductor element sealing resin, the sealing Because the resin flows out to the back side, there is a design restriction in that a back connection hole cannot be provided within the sealing area of the sealing resin. However, as semiconductor devices become more highly integrated, the device size increases, while the panocage shape tends to become smaller, so this design restriction has become a major obstacle.
また、ＩＣカードなどに使用される半導体装置において
は、パッケージ厚の薄型化が要求されるため、半導体素
子の封正方法としてトランスファモールドが用いられて
きたが、この封止樹脂領域内に裏面接続孔があることは
致命的であった．即ち、樹脂封止は半導体回路基板に裏
面接続孔をあけ、回路基板の表裏面及び裏面接続孔内に
配線をパターニングした後、半導体素子及び配線と接続
されるワイヤを含む所定領域で行うものである．このこ
とから考えて、樹脂封止する際に、回路基板の裏面に金
型（下金型）を当てておき、裏面接続孔の一方（下方）
開口部を塞いでおけば、裏面への樹脂の流れ出しは防止
できる．しかし、回路基板裏面の配線は外部機器との接
続端子となる部分であるため、外傷等があってはならず
、結局、裏面の配線に対しては金型から浮かせた状態で
行わなければならないものであった。In addition, in semiconductor devices used in IC cards and the like, transfer molding has been used as a sealing method for semiconductor elements because the package thickness is required to be thin. The presence of holes was fatal. In other words, resin encapsulation is performed in a predetermined area including the semiconductor element and the wires to be connected to the wiring after forming a connection hole on the back side of the semiconductor circuit board and patterning wiring on the front and back sides of the circuit board and inside the connection hole on the back side. be. Considering this, when sealing with resin, place a mold (lower mold) on the back side of the circuit board, and place one side (lower side) of the back side connection hole.
By blocking the opening, you can prevent the resin from flowing out to the back side. However, since the wiring on the back side of the circuit board is the connection terminal for external equipment, there must be no external damage, and in the end, the wiring on the back side must be done while floating from the mold. It was something.
本発明は、上記問題点を除去し、封止樹脂の封止領域内
に裏面接続孔が設けられていても、片面トランスファモ
ールドができ、更には、生産性、品質性から見ても優れ
た半導体装置及びその製造方法を提供することを目的と
する．
（課題を解決するための手段）
本発明は、上記目的を達成するために、半導体素子が搭
載された回路基板を具備する半導体装置において、半導
体素子の封止領域内に形成された回路基板の裏面接続孔
が印刷により塞がれる樹脂層を設けるようにしたもので
ある．
また、半導体素子が搭載された回路基板を具備する半導
体装置の製造方法において、回路基板に裏面接続孔を形
成する工程と、前記回路基板の表裏面及び裏面接続孔内
に配線をパターニングする工程と、前記回路基板の配線
上の所定領域にソルダレジストを印刷によって形成する
工程と、前記裏面接続孔の一方の開口部にソルダレジス
トを印刷して該開口部を塞ぐ工程と、前記回路基板の所
定部分に半導体素子を固着し、該半導体素子と前記回路
基板上の配線とをワイヤで接続した後、前記裏面接続孔
を含む領域で半導体素子及びワイヤを樹脂で封止する工
程とを施すようにしたものである。The present invention eliminates the above-mentioned problems, enables single-sided transfer molding even if a back side connection hole is provided in the sealing area of the sealing resin, and is also superior in terms of productivity and quality. The purpose is to provide semiconductor devices and their manufacturing methods. (Means for Solving the Problems) In order to achieve the above object, the present invention provides a semiconductor device including a circuit board on which a semiconductor element is mounted. A resin layer is provided to cover the connection hole on the back side by printing. Further, a method for manufacturing a semiconductor device including a circuit board on which a semiconductor element is mounted includes a step of forming a back surface connection hole in the circuit board, and a step of patterning wiring on the front and back surfaces of the circuit board and in the back surface connection hole. , a step of forming a solder resist on a predetermined area on the wiring of the circuit board by printing, a step of printing a solder resist on one opening of the back surface connection hole to close the opening, After fixing a semiconductor element to the part and connecting the semiconductor element and the wiring on the circuit board with a wire, a step of sealing the semiconductor element and the wire with a resin in a region including the back surface connection hole is performed. This is what I did.
（作用）
本発明によれば、上記したように、半導体素子搭載用回
路基板を有する半導体装置の製造方法において、裏面接
続孔にソルダレジストを２回塗布することにより、裏面
接続孔を塞ぐようにしたので、半導体素子を樹脂封止し
た時に、封止領域内に裏面接続孔が設けられていても、
樹脂が裏面に流れ出すことはない．そのため、パターン
設計が容易となり、パッケージ形状の小型化を図ること
ができる．また、回路基板の製造工程としては、ソルダ
レジスト塗布が１回増えるだけであり、安価に製造する
ことができる．
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Function) According to the present invention, as described above, in the method of manufacturing a semiconductor device having a circuit board for mounting a semiconductor element, the back side connection hole is covered by applying solder resist twice to the back side connection hole. Therefore, when a semiconductor element is sealed with resin, even if a back side connection hole is provided within the sealing area,
The resin will not flow out to the back side. Therefore, pattern design becomes easy and the package shape can be made smaller. In addition, the circuit board manufacturing process requires only one additional solder resist application, and can be manufactured at low cost. (Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体素子搭載用回路基
板を備えた半導体装置の製造工程断面図である．
まず、第１図（ａ）に示すように、回路基板２ｌに裏面
接続孔２２を形成する．
次に、第１図（ｂ）に示すように、回路基板２１の両面
及び裏面接続孔２２の壁面に化学銅メッキ及び電気銅メ
ッキ等のメッキ層２３を形成する。FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor device equipped with a circuit board for mounting semiconductor elements, showing an embodiment of the present invention. First, as shown in FIG. 1(a), a back connection hole 22 is formed in the circuit board 2l. Next, as shown in FIG. 1(b), a plating layer 23 such as chemical copper plating or electrolytic copper plating is formed on both surfaces of the circuit board 21 and the wall surface of the back surface connection hole 22.
次いで、第１図（ｃ）に示すように、回路基板２ｌにパ
ターンを形成する．ここで、２３′ は配線用導体、２
３”は裏面接続孔ランドである．次に、第１図（ｄ）に
示すように、回路基板２ｌにソルダレジスト２４を印刷
する．ここでは、配線導体の保護を行うために、原則と
して外部接続用端子及び電気的測定用端子以外の全てに
塗布する。Next, as shown in FIG. 1(c), a pattern is formed on the circuit board 2l. Here, 23' is a wiring conductor, 2
3" is the back surface connection hole land. Next, as shown in FIG. Apply to everything except connection terminals and electrical measurement terminals.
また、ソルダレジスト２４を両面に印刷する場合、裏面
接続孔２２を塞ぐ側において、その孔の部分にも塗布さ
れるようにレジストマスクを製作する．逆に反対側では
、裏面接続孔２２の部分にソルダレジスト２４が塗布さ
れないようにレジストマスクを製作する．
次に、第１図（ｅ）に示すように、回路基板２ｌの裏面
接続孔２２を塞ぐ側に、更にもう一度ソルダレジスト２
５を印刷する．
このように、裏面接続孔２２に同一のレジストマスクで
ソルダレジスト２４． ２５を２回印刷することにより
、裏面接続孔２２を完全にを塞ぐことができる．
最後に、第１図（ｆ）に示すように、回路基板２１にＮ
ｉ−Ａｕメッキによりメッキ層２６を形成する．第５図
は、本発明の他の実施例を示す半導体素子搭載用回路基
板を備えた半導体装置の製造工程断面図である。In addition, when printing the solder resist 24 on both sides, a resist mask is manufactured on the side that closes the back connection hole 22 so that it is applied to the hole portion as well. On the other hand, on the opposite side, a resist mask is manufactured so that the solder resist 24 is not applied to the back surface connection hole 22 portion. Next, as shown in FIG. 1(e), solder resist 2 is applied once again to the side that closes the back connection hole 22 of the circuit board 2l.
Print 5. In this way, the solder resist 24. By printing 25 twice, the back side connection hole 22 can be completely closed. Finally, as shown in FIG. 1(f), the circuit board 21 is
A plating layer 26 is formed by i-Au plating. FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device equipped with a circuit board for mounting a semiconductor element, showing another embodiment of the present invention.
第５図（ａ）〜（Ｃ）までは、第１図に示すものと同し
製造工程である．
次いで、第５図（ｄ）に示すように、配線用導体２３′
、裏面接続孔ランド２３′にＮｉ−Ａｕメッキを施し、
メッキ層３１を形成する．
次に、第５図（ｅ）に示すように、回路基板２ｌにソル
ダレジスト３２を印刷する．
次に、第５図（ｆ）に示すように、回路基板２１の裏面
接続孔２２を塞ぐ側に、更にもう一度ソルダレジスト３
３を印刷して、裏面接続孔２２を塞ぐ．第６図は本発明
の更なる他の実施例を示す半導体素子搭載用回路基板を
備えた半導体装置の製造工程断面図である．
第６図（ａ）〜（ｃ）までは、第１図に示すものと同じ
製造工程である．
次いで、第６図（ｄ）に示すように、回路基板２１にソ
ルダレジスト４１を印刷する．
次に、第６図（ｅ）に示すように、回路基板２１にＮｉ
−Ａｕメッキを施し、メッキ層４２を形成する．次に、
第６図（ｆ）に示すように、回路基！ＩＩｉ２１の裏面
接続孔２２を塞ぐ側に、更にもう一度ソルダレジスト４
３を印刷して、裏面接続孔２２を塞ぐ。5(a) to 5(C) are the same manufacturing steps as shown in FIG. 1. Next, as shown in FIG. 5(d), the wiring conductor 23'
, Ni-Au plating is applied to the back side connection hole land 23',
A plating layer 31 is formed. Next, as shown in FIG. 5(e), a solder resist 32 is printed on the circuit board 2l. Next, as shown in FIG. 5(f), solder resist 3 is applied once again to the side that closes the back connection hole 22 of the circuit board 21.
3 and close the connection hole 22 on the back side. FIG. 6 is a sectional view showing a manufacturing process of a semiconductor device equipped with a circuit board for mounting semiconductor elements, showing still another embodiment of the present invention. 6(a) to 6(c) are the same manufacturing steps as shown in FIG. 1. Next, as shown in FIG. 6(d), a solder resist 41 is printed on the circuit board 21. Next, as shown in FIG. 6(e), Ni is placed on the circuit board 21.
- Apply Au plating to form the plating layer 42. next,
As shown in Figure 6(f), the circuit board! Apply solder resist 4 again on the side that closes the back connection hole 22 of IIi21.
3 to close the back connection hole 22.
第７図は本発明の実施例を示す半導体素子搭載用回路基
板を備えた半導体装置の断面図である．この図に示すよ
うに、半導体素子５５が搭載された回路基板５０を具備
する半導体装置において、半導体素子５５の樹脂封止５
７領域内に形成された回路基板５０の裏面接続孔５ｌを
、印刷により樹脂層５４で塞いでいる．ここで、樹脂層
５４がエポキシ系絶縁樹脂であり、その粘度が１００〜
３００ ｐｓ，裏面接続孔５１の孔径がφ１．０■以下
、回路基板の板厚０．３一以上であれば、上述の印刷方
式で十分に裏面接続孔５ｌを塞ぐことができる．なお、
ここで、５２．５３は配線導体、５６はワイヤである．
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない．
（発明の効果）
以上、詳細に説明したように、本発明によれば、次のよ
うな効果を奏することができる．（１）半導体素子の樹
脂封止領域内に裏面接続孔を設けることができるように
なるため、パターン設計が容易となり、パッケージ形状
の小型化を図ることができる．
（２）裏面接続孔の内壁はメッキされているため、品質
面から見ても優れている．
（３）回路基板の製造工程としては、ソルダレジスト塗
布が１回増えるだけであり、安価に製造でき、しかも生
産性の向上を図ることができる。FIG. 7 is a sectional view of a semiconductor device equipped with a circuit board for mounting semiconductor elements, showing an embodiment of the present invention. As shown in this figure, in a semiconductor device including a circuit board 50 on which a semiconductor element 55 is mounted, resin sealing 5 of the semiconductor element 55 is
The back side connection holes 5l of the circuit board 50 formed in the 7 areas are covered with a resin layer 54 by printing. Here, the resin layer 54 is an epoxy-based insulating resin, and its viscosity is 100 to
300 ps, the diameter of the back side connecting hole 51 is φ1.0 mm or less, and the board thickness of the circuit board is 0.3 mm or more, the back side connecting hole 5l can be sufficiently closed by the above-described printing method. In addition,
Here, 52 and 53 are wiring conductors, and 56 is a wire.
Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention. (Effects of the Invention) As described above in detail, according to the present invention, the following effects can be achieved. (1) Since it becomes possible to provide a backside contact hole within the resin-sealed area of the semiconductor element, pattern design becomes easier and the package shape can be made smaller. (2) The inner wall of the back connection hole is plated, so it is superior in terms of quality. (3) In the manufacturing process of the circuit board, only one additional solder resist application is required, and the manufacturing process can be performed at low cost and productivity can be improved.
（４）トランスファモールド時の圧力にも十分耐え得る
ため、薄型化パッケージの製造が可能となる。(4) It can sufficiently withstand pressure during transfer molding, making it possible to manufacture thinner packages.
（５）裏面接続孔からの樹脂漏れがないため、歩留まり
が向上する．(5) Yield is improved because there is no resin leakage from the back side connection hole.
第１図は本発明の実施例を示す半導体素子搭載用回路基
板を備えた半導体装置の製造工程断面図、第２図は従来
の半導体素子搭載用回路基板を備えた半導体装置の部分
平面図、第３図はその半導体装置の断面図、第４図はそ
の半導体装置の裏面接続孔の拡大断面図、第５図は本発
明の他の実施例を示す半導体素子搭載用回路基板を備え
た半導体装置の製造工程断面図、第６図は本発明の更な
る他の実施例を示す半導体素子搭載用回路基板を傭えた
半導体装置の製造工程断面図、第７図は本発明の実施例
を示す半導体素子搭載用回路基板を備えた半導体装置の
断面図である．
２１． ５０・・・回路基板、２２． ５１・・・裏面
接続孔（スルーホール’） 、２３， ２６， ３１．
４２・・・メッキ層、２３′・・・配線用導体、２３
″・・・裏面接続孔ランド、２４． ２５，３２， ３
３． ４１． ４３・・・ソルダレジスト、５２． ５
３・・・配線導体、５４・・・樹脂層、５５・・・半導
体素子、５６・・・ワイヤ、５７・・・樹脂封止．FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device equipped with a circuit board for mounting semiconductor elements showing an embodiment of the present invention, and FIG. 2 is a partial plan view of a conventional semiconductor device equipped with a circuit board for mounting semiconductor elements. FIG. 3 is a sectional view of the semiconductor device, FIG. 4 is an enlarged sectional view of the back side connection hole of the semiconductor device, and FIG. 5 is a semiconductor device equipped with a circuit board for mounting a semiconductor element, showing another embodiment of the present invention. 6 is a cross-sectional view of the manufacturing process of the device, and FIG. 6 is a cross-sectional view of the manufacturing process of a semiconductor device using a circuit board for mounting semiconductor elements, showing still another embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device, showing an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device equipped with a circuit board for mounting semiconductor elements. 21. 50... circuit board, 22. 51... Back side connection hole (through hole'), 23, 26, 31.
42... Plated layer, 23'... Wiring conductor, 23
″...Back side connection hole land, 24. 25, 32, 3
3. 41. 43...Solder resist, 52. 5
3... Wiring conductor, 54... Resin layer, 55... Semiconductor element, 56... Wire, 57... Resin sealing.
Claims (5)
体装置において、 半導体素子の封止領域内に形成された回路基板の裏面接
続孔が印刷により塞がれる樹脂層を有することを特徴と
する半導体装置。(1) A semiconductor device equipped with a circuit board on which a semiconductor element is mounted, characterized by having a resin layer in which a back side connection hole of the circuit board formed in the sealing area of the semiconductor element is closed by printing. Semiconductor equipment.
体装置の製造方法において、 （ａ）回路基板に裏面接続孔を形成する工程と、（ｂ）
前記回路基板の表裏面及び裏面接続孔内に配線をパター
ニングする工程と、 （ｃ）前記回路基板の配線上の所定領域にソルダレジス
トを印刷によって形成する工程と、 （ｄ）前記裏面接続孔の一方の開口部にソルダレジスト
を印刷して該開口部を塞ぐ工程と、 （ｅ）前記回路基板の所定部分に半導体素子を固着し、
該半導体素子と前記回路基板上の配線とをワイヤで接続
した後、前記裏面接続孔を含む領域で半導体素子及びワ
イヤを樹脂で封止する工程とを有する半導体装置の製造
方法。(2) A method for manufacturing a semiconductor device including a circuit board on which a semiconductor element is mounted, including (a) forming a back surface connection hole in the circuit board, and (b)
(c) forming a solder resist in a predetermined area on the wiring of the circuit board by printing; (d) forming the wiring in the back surface connection hole; (e) fixing a semiconductor element to a predetermined portion of the circuit board;
A method for manufacturing a semiconductor device, comprising the step of connecting the semiconductor element and the wiring on the circuit board with a wire, and then sealing the semiconductor element and the wire with a resin in a region including the back surface connection hole.
体装置の製造方法において、 （ａ）回路基板に裏面接続孔を形成する工程と、（ｂ）
前記回路基板の表裏面及び裏面接続孔内に配線をパター
ニングする工程と、 （ｃ）前記回路基板の配線上の所定領域にソルダレジス
トを印刷によって形成する工程と、 （ｄ）前記裏面接続孔の一方の開口部にソルダレジスト
を印刷して該開口部を塞ぐ工程と、 （ｅ）前記裏面接続孔内の配線にＮｉ−Ａｕメッキを施
す工程と、 （ｆ）前記回路基板の所定部分に半導体素子を固着し、
該半導体素子と前記回路基板上の配線とをワイヤで接続
した後、前記裏面接続孔を含む領域で半導体素子及びワ
イヤを樹脂で封止する工程とを有する半導体装置の製造
方法。(3) A method for manufacturing a semiconductor device including a circuit board on which a semiconductor element is mounted, including (a) forming a back surface connection hole in the circuit board, and (b)
(c) forming a solder resist in a predetermined area on the wiring of the circuit board by printing; (d) forming the wiring in the back surface connection hole of the circuit board; (e) plating the wiring in the back side connection hole with Ni-Au plating; (f) applying a semiconductor to a predetermined portion of the circuit board; Fix the element,
A method for manufacturing a semiconductor device, comprising the step of connecting the semiconductor element and the wiring on the circuit board with a wire, and then sealing the semiconductor element and the wire with a resin in a region including the back surface connection hole.
体装置の製造方法において、 （ａ）回路基板に裏面接続孔を形成する工程と、（ｂ）
前記回路基板の表裏面及び裏面接続孔内に配線をパター
ニングする工程と、 （ｃ）配線全体にＮｉ−Ａｕメッキを施す工程と、（ｄ
）前記回路基板の前記配線上の所定領域にソルダレジス
トを印刷によって形成する工程と、（ｅ）前記裏面接続
孔の一方の開口部にソルダレジストを印刷して該開口部
を塞ぐ工程と、 （ｆ）前記回路基板の所定部分に半導体素子を固着し、
該半導体素子と回路基板上の配線とをワイヤで接続した
後、前記裏面接続孔を含む領域で半導体素子及びワイヤ
を樹脂で封止する工程とを有する半導体装置の製造方法
。(4) A method for manufacturing a semiconductor device including a circuit board on which a semiconductor element is mounted, including (a) forming a back surface connection hole in the circuit board, and (b)
a step of patterning wiring on the front and back surfaces of the circuit board and inside the connection holes on the back side; (c) a step of applying Ni-Au plating to the entire wiring; and (d)
) forming a solder resist on a predetermined area on the wiring of the circuit board by printing; (e) printing a solder resist on one opening of the back surface connection hole to close the opening; f) fixing a semiconductor element to a predetermined portion of the circuit board;
A method for manufacturing a semiconductor device, comprising the step of connecting the semiconductor element and wiring on a circuit board with a wire, and then sealing the semiconductor element and the wire with a resin in a region including the back surface connection hole.
体装置の製造方法において、 （ａ）回路基板に裏面接続孔を形成する工程と、（ｂ）
前記回路基板の表裏面及び裏面接続孔内に配線をパター
ニングする工程と、 （ｃ）前記回路基板の配線上の所定領域にソルダレジス
トを印刷によって形成する工程と、 （ｄ）前記裏面接続孔内の配線にＮｉ−Ａｕメッキを施
す工程と、 （ｅ）前記裏面接続孔の一方の開口部にソルダレジスト
を印刷して該開口部を塞ぐ工程と、 （ｆ）前記回路基板の所定部分に半導体素子を固着し、
該半導体素子と回路基板上の配線とをワイヤで接続した
後、前記裏面接続孔を含む領域で半導体素子及びワイヤ
を樹脂で封止する工程とを有する半導体装置の製造方法
。(5) A method for manufacturing a semiconductor device including a circuit board on which a semiconductor element is mounted, including (a) forming a back surface connection hole in the circuit board, and (b)
(c) forming a solder resist in a predetermined area on the wiring of the circuit board by printing; (d) inside the back connection hole. (e) printing a solder resist on one opening of the back surface connection hole to close the opening; (f) applying a semiconductor to a predetermined portion of the circuit board; Fix the element,
A method for manufacturing a semiconductor device, comprising the step of connecting the semiconductor element and wiring on a circuit board with a wire, and then sealing the semiconductor element and the wire with a resin in a region including the back surface connection hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309085A JP2925609B2 (en) | 1989-11-30 | 1989-11-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309085A JP2925609B2 (en) | 1989-11-30 | 1989-11-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03171760A true JPH03171760A (en) | 1991-07-25 |
| JP2925609B2 JP2925609B2 (en) | 1999-07-28 |
Family
ID=17988706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1309085A Expired - Fee Related JP2925609B2 (en) | 1989-11-30 | 1989-11-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2925609B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325242B1 (en) * | 1998-05-15 | 2002-04-17 | 이택렬 | Semiconductor device and fabricating method thereof |
| US6737740B2 (en) * | 2001-02-08 | 2004-05-18 | Micron Technology, Inc. | High performance silicon contact for flip chip |
| US6962866B2 (en) | 2000-03-02 | 2005-11-08 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
| WO2019072575A1 (en) * | 2017-10-10 | 2019-04-18 | Conti Temic Microelectronic Gmbh | Method for producing an electronic component |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61147595A (en) * | 1984-12-21 | 1986-07-05 | 大日本インキ化学工業株式会社 | Manufacture of double side printed wiring board |
| JPS63244631A (en) * | 1987-03-30 | 1988-10-12 | Nec Corp | Manufacture of hybrid integrated circuit device |
| JPH01165495A (en) * | 1987-12-22 | 1989-06-29 | Dainippon Printing Co Ltd | Ic card and ic module for ic card |
-
1989
- 1989-11-30 JP JP1309085A patent/JP2925609B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61147595A (en) * | 1984-12-21 | 1986-07-05 | 大日本インキ化学工業株式会社 | Manufacture of double side printed wiring board |
| JPS63244631A (en) * | 1987-03-30 | 1988-10-12 | Nec Corp | Manufacture of hybrid integrated circuit device |
| JPH01165495A (en) * | 1987-12-22 | 1989-06-29 | Dainippon Printing Co Ltd | Ic card and ic module for ic card |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325242B1 (en) * | 1998-05-15 | 2002-04-17 | 이택렬 | Semiconductor device and fabricating method thereof |
| US6962866B2 (en) | 2000-03-02 | 2005-11-08 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
| US6984886B2 (en) | 2000-03-02 | 2006-01-10 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
| US7294921B2 (en) | 2000-03-02 | 2007-11-13 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
| US6737740B2 (en) * | 2001-02-08 | 2004-05-18 | Micron Technology, Inc. | High performance silicon contact for flip chip |
| US6812137B2 (en) | 2001-02-08 | 2004-11-02 | Micron Technology, Inc. | Method of forming coaxial integrated circuitry interconnect lines |
| US6828656B2 (en) | 2001-02-08 | 2004-12-07 | Micron Technology, Inc. | High performance silicon contact for flip chip and a system using same |
| WO2019072575A1 (en) * | 2017-10-10 | 2019-04-18 | Conti Temic Microelectronic Gmbh | Method for producing an electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2925609B2 (en) | 1999-07-28 |
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