KR970030707A - Semiconductor package with external leads attached to the surface - Google Patents

Semiconductor package with external leads attached to the surface Download PDF

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Publication number
KR970030707A
KR970030707A KR1019950041027A KR19950041027A KR970030707A KR 970030707 A KR970030707 A KR 970030707A KR 1019950041027 A KR1019950041027 A KR 1019950041027A KR 19950041027 A KR19950041027 A KR 19950041027A KR 970030707 A KR970030707 A KR 970030707A
Authority
KR
South Korea
Prior art keywords
semiconductor package
reduced
exposed
circuit board
printed circuit
Prior art date
Application number
KR1019950041027A
Other languages
Korean (ko)
Inventor
이진혁
이태구
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950041027A priority Critical patent/KR970030707A/en
Publication of KR970030707A publication Critical patent/KR970030707A/en

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 칩 패키지에 관한 것으로, 더욱 상세하게는 반도체 칩 패키지를 형성할 때 외부리드가 성형수지의 일측면에 부착 노출되어 인쇄회로기판에 탑재시 박형화를 이룰 수 있는 외부리드가 표면에 노출된 반도체 패키지에 관한 것이다. 본 발명은, 외부리드가 성형수지의 하부층의 상면에 노출되어 있고, 상기 외부리드가 하부층의 일단의 끝까지 신장되어 있고 상부층은 외부리드의 끝단에서 칩의 중앙방향으로 소정거리 이격되어 성형된 것을 특징으로 하는 외부리드가 표면에 노출된 반도체 패키지를 제공한다.The present invention relates to a semiconductor chip package, and more particularly, when the semiconductor chip package is formed, an external lead is exposed to one side of the molding resin and exposed to the surface of the external lead, which can be thinned when mounted on a printed circuit board. To a semiconductor package. The present invention is characterized in that the outer lead is exposed to the upper surface of the lower layer of the molding resin, the outer lead is extended to the end of one end of the lower layer and the upper layer is formed by being spaced a predetermined distance away from the end of the outer lead toward the center of the chip. Provided is a semiconductor package in which an external lead is exposed on a surface.

따라서, 본 발명에 따른 구조에 의하면, 반도체 패키지를 인쇄회로기판에 탑재시 전체적인 두께가 감소되는 효과가 있고, 패키징시 리드 프레임의 포밍공정이 줄어들어 제품의 생산이 빠르게 됨과 동시에 외부리드에 의한 불량이 방지되는 효과가 있으며, 반도체 패키지 상부면이 인쇄회로기판에 접착시 열방출효과가 있다. 또한, 인쇄회로기판상에서 반도체 패키지의 외부리드가 차지하는 면적이 감소됨으로 모듈의 집적도가 증가하는 장점이 있고, 성형수지의 양이 적어짐과 동시에 가격이 저렴해 지는 효과가 있다.Therefore, according to the structure according to the present invention, when the semiconductor package is mounted on the printed circuit board, the overall thickness is reduced, and the packaging process of the lead frame is reduced during packaging, so that the production of the product is fast and the defects caused by external leads are reduced. There is an effect that is prevented, the heat dissipation effect when the upper surface of the semiconductor package is bonded to the printed circuit board. In addition, since the area occupied by the external lead of the semiconductor package on the printed circuit board is reduced, the degree of integration of the module is increased, and the amount of molding resin is reduced and the price is reduced.

Description

외부리드가 표면에 부착 노출된 반도체 패키지Semiconductor package with external leads attached to the surface

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2도는 본 발명의 반도체 패키지를 이용하여 적층한 상태를 나타내는 단면도.2 is a cross-sectional view showing a state of being laminated using the semiconductor package of the present invention.

Claims (1)

외부리드가 성형수지의 하부층의 상면에 노출되어 있고, 상기 외부리드가 하부층의 일단의 끝까지 신장되어 있고 상부층은 외부리드와 끝단에서 칩의 중앙방향으로 소정거리 이격되어 성형된 것을 특징으로 하는 외부리드가 표면에 노출된 반도체 패키지.The outer lead is exposed to the upper surface of the lower layer of the molding resin, the outer lead is extended to the end of one end of the lower layer and the upper layer is formed by being spaced apart a predetermined distance in the direction of the center of the chip from the outer lead and the end Semiconductor package with exposed surface. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950041027A 1995-11-13 1995-11-13 Semiconductor package with external leads attached to the surface KR970030707A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950041027A KR970030707A (en) 1995-11-13 1995-11-13 Semiconductor package with external leads attached to the surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950041027A KR970030707A (en) 1995-11-13 1995-11-13 Semiconductor package with external leads attached to the surface

Publications (1)

Publication Number Publication Date
KR970030707A true KR970030707A (en) 1997-06-26

Family

ID=66587713

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950041027A KR970030707A (en) 1995-11-13 1995-11-13 Semiconductor package with external leads attached to the surface

Country Status (1)

Country Link
KR (1) KR970030707A (en)

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