KR940010292A - Semiconductor package - Google Patents

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Publication number
KR940010292A
KR940010292A KR1019920020467A KR920020467A KR940010292A KR 940010292 A KR940010292 A KR 940010292A KR 1019920020467 A KR1019920020467 A KR 1019920020467A KR 920020467 A KR920020467 A KR 920020467A KR 940010292 A KR940010292 A KR 940010292A
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KR
South Korea
Prior art keywords
semiconductor
leads
semiconductor package
package
semiconductor chips
Prior art date
Application number
KR1019920020467A
Other languages
Korean (ko)
Other versions
KR100216061B1 (en
Inventor
권희준
김재준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920020467A priority Critical patent/KR100216061B1/en
Publication of KR940010292A publication Critical patent/KR940010292A/en
Application granted granted Critical
Publication of KR100216061B1 publication Critical patent/KR100216061B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

두개의 반도체 칩이 정면을 마주보도록 적층되는 반도체 패키지에서, 제1 및 제2리이드들이 각각 한방향으로 연결되어 있는 제1 및 제2반도체 칩이 있다. 상기 제1리이드들은 한방향 예를들어 좌.우 방향으로 연장되어 있으며, 상기 제1반도체 칩과 정면을 마주보도록 적층되는 제2반도체 칩은 상기 제2리이드들이 상기 제1리이드들과 교차되는 방향 예를들어 상, 하 방향으로 향하도록 하여 상기 제1 및 제2리이드들이 사방으로 돌출되어 적층된다. 이때 상기 제1 및 제2반도체 칩의 사이에는 접착테이프가 개재되어 있는 상기 반도체칩들을 접착시키며, 표면의 손상을 방지한다.In a semiconductor package in which two semiconductor chips are stacked to face each other, there are first and second semiconductor chips having first and second leads connected in one direction, respectively. The first leads extend in one direction, for example, in a left and right direction, and a second semiconductor chip which is stacked to face the first semiconductor chip in the front direction is a direction in which the second leads cross the first leads. For example, the first and second leads protrude in all directions and are stacked to face upward and downward. In this case, the semiconductor chips having the adhesive tape interposed therebetween are bonded between the first and second semiconductor chips, thereby preventing surface damage.

따라서 밀러 칩을 형성하는 등의 별도의 추가 공정이 없어 반도체 패키지의 제조공정이 간단하며, 반도체 패키지의 두께 증가 없이 반도체 패키지의 실장밀도를 향상시킬 수 있다. 또한 반도체 패키지의 실장완료 후 상기 반도체 패키지의 신뢰성 확인 및 교환이 용이하다. 또한 상기 리이드들 상호간의 접합이 필요없이 반도체 패키지의 신뢰성을 향상시킬 수 있다.Therefore, there is no additional process of forming a Miller chip, thereby simplifying the manufacturing process of the semiconductor package, and improving the mounting density of the semiconductor package without increasing the thickness of the semiconductor package. In addition, it is easy to check and replace the reliability of the semiconductor package after mounting the semiconductor package. In addition, the reliability of the semiconductor package can be improved without the need for bonding between the leads.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 이 발명의 일 실시예에 따른 반도체 패키지를 나타내는 도면,3 is a view showing a semiconductor package according to an embodiment of the present invention;

제4도는 이 발명의 다른 실시예에 따른 반도체 패키지를 나타내는 도면이다.4 is a view showing a semiconductor package according to another embodiment of the present invention.

Claims (6)

제1 및 제2반도체 칩의 각각의 본딩패드들과 연결되는 제1 및 제2리이드들을 구비하여 상기 제1 및 제2반도체 칩의 정면이 마주보도록 적층되는 반도체 패키지에 있어서, 상기 제1 및 제2반도체 칩의 사이에 접착층들이 개재되어 접착되며, 상기 제1리이드들과 상기 제2리이드들이 교차되는 방향으로 상기 제 1반도체 칩상에 제2반도체 칩상에 탑재되는 반도체 패키지.A semiconductor package having first and second leads connected to respective bonding pads of first and second semiconductor chips, wherein the front surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are stacked. A semiconductor package is bonded between two semiconductor chips with an adhesive layer interposed therebetween, and mounted on the second semiconductor chip on the first semiconductor chip in a direction in which the first leads and the second leads cross each other. 제1항에 있어서, 상기 접착층이 절연성의 접착테이프로 되는 반도체 패키지.The semiconductor package of claim 1, wherein the adhesive layer is an insulating adhesive tape. 제1항에 있어서, 상기 접착층이 상기 제1 및 제2리이드들이 연결되어 있지않은 제1 및 제2반도체 칩의 상부에 각각 형성되어 있는 반도체 패키지.The semiconductor package of claim 1, wherein the adhesive layer is formed on the first and second semiconductor chips to which the first and second leads are not connected, respectively. 제1항에 있어서, 상기 제1 및 제2반도체 칩을 감싸 보호하는 몰딩수지로 형성되어 있는 보호층을 별도로 구비하는 반도체 패키지.The semiconductor package of claim 1, further comprising a protective layer formed of a molding resin surrounding and protecting the first and second semiconductor chips. 제1항에 있어서, 상기 제1 및 제2리이드들이 프렉시블한 탭형의 리이드들로 형성되어 있는 반도체 패키지.The semiconductor package of claim 1, wherein the first and second leads are formed of flexible tab-shaped leads. 제1항에 있어서, 상기 제1 및 제2반도체 칩이 직사각형일 경우 상기 제2반도체 칩의 하부면과 실장되는 기판 사이의 공간을 절연수지로 메워 상기 제2반도체 칩이 안정되게 실장되도록 하는 반도체 패키지.The semiconductor of claim 1, wherein when the first and second semiconductor chips are rectangular, a space between the lower surface of the second semiconductor chip and the substrate to be mounted is filled with an insulating resin so that the second semiconductor chip is stably mounted. package. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020467A 1992-10-31 1992-10-31 Semiconductor package KR100216061B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920020467A KR100216061B1 (en) 1992-10-31 1992-10-31 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020467A KR100216061B1 (en) 1992-10-31 1992-10-31 Semiconductor package

Publications (2)

Publication Number Publication Date
KR940010292A true KR940010292A (en) 1994-05-24
KR100216061B1 KR100216061B1 (en) 1999-08-16

Family

ID=19342363

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020467A KR100216061B1 (en) 1992-10-31 1992-10-31 Semiconductor package

Country Status (1)

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KR (1) KR100216061B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3825943B2 (en) * 1999-09-06 2006-09-27 株式会社東芝 Semiconductor package and printed wiring board for semiconductor package
KR100779344B1 (en) * 2001-04-20 2007-11-23 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Also Published As

Publication number Publication date
KR100216061B1 (en) 1999-08-16

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