KR930014890A - Self-aligned silicide formation method - Google Patents

Self-aligned silicide formation method Download PDF

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Publication number
KR930014890A
KR930014890A KR1019910023298A KR910023298A KR930014890A KR 930014890 A KR930014890 A KR 930014890A KR 1019910023298 A KR1019910023298 A KR 1019910023298A KR 910023298 A KR910023298 A KR 910023298A KR 930014890 A KR930014890 A KR 930014890A
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South Korea
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gate
depositing
high melting
forming
self
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KR1019910023298A
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Korean (ko)
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KR940007459B1 (en
Inventor
윤규한
노태훈
박승현
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문정환
금성일렉트론 주식회사
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Priority to KR1019910023298A priority Critical patent/KR940007459B1/en
Publication of KR930014890A publication Critical patent/KR930014890A/en
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Publication of KR940007459B1 publication Critical patent/KR940007459B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

본 발명은 자기 정렬 실리사이드(Self Aligned Silicide) 형성방법에 관한 것으로, 특히 고속 동작을 필요로하는 회로에 적용되는 실리사이드 형성방법에 관한 것이다. 이를 위하여 본 발명에서는, 자기정렬 실리사이드 형성방법에 있어서, 실리콘 기판에 게이트 산화막, 게이트로 사용될 폴리실리콘 및 질화막을 차례로 중착시키고, 포토/에치 공정을 거쳐 게이트를 패터닝하는 단계(a)와, 산화막을 중착하여 게이트 사이드 웰 스페이서를 형성하고 게이트 상의 질화막을 제거하고 고융점 금속을 중착시키는 단계(b)와, 열처리하여 고융점 금속과 실리콘 또는 폴리 실리콘이 접초하고 있는 게이트 폴리실리콘 위와 트랜지스터의 소스/드레인 위에만 실리사이드를 형성하고, 습식식각하여 고융점 금속을 제거하여 단계(c)를 포함하는 것을 특징으로 하는 자기정렬 실리사이드 형성방법.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming self aligned silicides, and more particularly, to a method of forming silicides applied to a circuit requiring high speed operation. To this end, in the present invention, in the method for forming a self-aligned silicide, a step of (a) and intermediately depositing a gate oxide film, a polysilicon to be used as a gate and a nitride film on a silicon substrate, patterning the gate through a photo / etch process, and the oxide film (B) depositing a gate side well spacer to remove the nitride film on the gate and depositing a high melting point metal, and performing heat treatment to form the gate polysilicon and the source / drain of the transistor on the gate of the high melting point metal and silicon or polysilicon. Forming a silicide only thereon and removing the high melting point metal by wet etching to form a self-aligned silicide forming method.

Description

자기정렬 실리사이드 형성방법Self-aligned silicide formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도는 본 발명의 자기정렬 실리사이드 형성 공정도.2 is a process diagram for forming a self-aligned silicide of the present invention.

제 3 도는 본 발명의 다른 실시예도.3 is another embodiment of the present invention.

Claims (2)

자기정렬 실리사이드 형성방법에 있어서, 실리콘 기판에 게이트 산화막, 게이트로 사용될 폴리실리콘 및 질화막을 차례로 증착시키고, 포토/에치 공정을 거쳐 게이트를 패터닝하는 단계(a)와, 산화막을 증착하여 게이트 사이드 월 스페이서를 형성하고 게이트 상의 질화막을 제거하고 고융점 금속을 증착시키는 단계(b)와, 열처리하여 고융점 금속과 실리콘 또는 폴리실리콘이 접촉하고 있는 게이트 폴리실리콘 위와 트랜지스터의 소스/드레인 위에만 실리사이드를 형성하고, 습식식각하여 고융점 금속을 제거하는 단계(C)를 포함하는 것을 특징으로 하는 자기정렬 실리사이드 형성방법.A method of forming a self-aligned silicide, comprising depositing a gate oxide film, a polysilicon to be used as a gate, and a nitride film on a silicon substrate in turn, patterning the gate through a photo / etch process, and depositing an oxide film to form a gate sidewall spacer. (B) removing the nitride film on the gate and depositing a high melting point metal, and performing heat treatment to form silicide only on the gate polysilicon in contact with the high melting point metal and silicon or polysilicon and on the source / drain of the transistor. And (C) removing the high melting point metal by wet etching. 자기정렬 실리사이드 형성방법에 있어서, 실리콘 기판에 게이트 산화막, 게이트로 사용될 폴리실리콘 및 질화막을 차례로 증착시키고, 포토/에치 공정을 거쳐 게이트를 패터닝하는 단계(a)와, 산화막을 증착하여 게이트 사이드 월 스페이서를 형성하고 게이트 상의 질화막을 제거하고 고융점 금속을 증착시키는 단계(b)와, 포토 레지스트를 두껍게 코팅한 후 게이트 측벽에 형성된 사이드 월 스페이서 상부가 포토 레지스트 위로 돌출되도록 에치백하여 표면을 평탄화 시키는 단계(c)와, 포토 레지스트 위로 돌출된 고융점 금속 및 산화막 사이드 월 스페이서를 차례로 식각하는 단계(d)와, 포토 레지스트를 제거하고 열처리를 실시하여 실리사이드를 형성하고 고융점 금속을 제거하는 단계(e)를 포함하는 것을 특징으로 하는 자기정렬 실리사이드 형성방법.A method of forming a self-aligned silicide, comprising depositing a gate oxide film, a polysilicon to be used as a gate, and a nitride film on a silicon substrate in turn, patterning the gate through a photo / etch process, and depositing an oxide film to form a gate sidewall spacer. (B) forming a film, removing a nitride film on the gate, and depositing a high melting point metal, and thickening the photoresist, and then etching back so that the top of the sidewall spacer formed on the gate sidewall protrudes over the photoresist to planarize the surface. (c) sequentially etching the high melting metal and the oxide sidewall spacers protruding over the photoresist, and removing the photoresist and performing a heat treatment to form silicide and remove the high melting metal (e). Self-aligned silicide forming method comprising a). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023298A 1991-12-18 1991-12-18 Forming method of silicide using self-align technique KR940007459B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023298A KR940007459B1 (en) 1991-12-18 1991-12-18 Forming method of silicide using self-align technique

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Application Number Priority Date Filing Date Title
KR1019910023298A KR940007459B1 (en) 1991-12-18 1991-12-18 Forming method of silicide using self-align technique

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KR930014890A true KR930014890A (en) 1993-07-23
KR940007459B1 KR940007459B1 (en) 1994-08-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605511B1 (en) * 2004-09-21 2006-07-28 삼성전자주식회사 Methods of forming at least one metal gate pattern in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605511B1 (en) * 2004-09-21 2006-07-28 삼성전자주식회사 Methods of forming at least one metal gate pattern in a semiconductor device

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KR940007459B1 (en) 1994-08-18

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