KR940007459B1 - Forming method of silicide using self-align technique - Google Patents
Forming method of silicide using self-align technique Download PDFInfo
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- KR940007459B1 KR940007459B1 KR1019910023298A KR910023298A KR940007459B1 KR 940007459 B1 KR940007459 B1 KR 940007459B1 KR 1019910023298 A KR1019910023298 A KR 1019910023298A KR 910023298 A KR910023298 A KR 910023298A KR 940007459 B1 KR940007459 B1 KR 940007459B1
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- South Korea
- Prior art keywords
- gate
- high melting
- silicide
- melting point
- polysilicon
- Prior art date
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 17
- 230000008018 melting Effects 0.000 claims abstract description 20
- 238000002844 melting Methods 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims 2
- 230000003472 neutralizing effect Effects 0.000 claims 1
- 230000008719 thickening Effects 0.000 claims 1
- 230000008016 vaporization Effects 0.000 abstract 2
- 238000009834 vaporization Methods 0.000 abstract 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제 1 도는 종래의 자기정렬 실리사이드 형성 공정도.1 is a conventional self-aligned silicide formation process diagram.
제 2 도는 본 발명의 자기정렬 실리사이드 형성 공정도.2 is a process diagram for forming a self-aligned silicide of the present invention.
제 3 도는 본 발명의 다른 실시예도.3 is another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 게이트 산화막11 silicon substrate 12 gate oxide film
13 : 게이트용 폴리실리콘 14 : 질화막13 polysilicon for gate 14 nitride film
15 : 사이드 월 스페이서 16 : 고융점 금속15: side wall spacer 16: high melting point metal
17 : 실리사이드 18 : 포토 레지스트17 silicide 18 photoresist
본 발명은 자기 정렬 실리사이드(Self Aligned Silicide) 형성방법에 관한 것으로, 특히 고속 동작을 필요로 하는 회로에 적용되는 실리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming self aligned silicides, and more particularly, to a method of forming silicides applied to a circuit requiring high speed operation.
종래의 자기정렬 실리사이드 형성공정을 보면 다음과 같다.A conventional self-aligned silicide forming process is as follows.
먼저 제 1 도의 a와 같이, 실리콘 기판(1)위에 필드 산화막(2)을 형성하고, 게이트 산화막(3)을 성장시킨 다음 게이트로 사용될 폴리실리콘(4)을 중착한다. 계속해서 게이트 마스크에 의해 포토/에치 공정으로 게이트 패터닝을 하고 산화막을 중착시킨 다음 비등방성 건식식각으로 게이트 측벽에 사이드 월 스페이서(5)를 형성한다.First, as shown in FIG. 1A, the field oxide film 2 is formed on the silicon substrate 1, the gate oxide film 3 is grown, and the polysilicon 4 to be used as a gate is deposited. Subsequently, gate patterning is performed by a gate mask in a photo / etch process, an oxide film is neutralized, and sidewall spacers 5 are formed on the sidewalls of the gate by anisotropic dry etching.
이어서 제 1 도의 b와 같이, 티타늄과 같은 고융점 금속(6)을 전면에 증착시킨다. 그후 제 1 도의 c와 같이 열처리하여 고융점 금속(6)과 실리콘 또는 폴리실리콘을 반응시키므로 게이트 위와 소스/드레인 위에 실리사이드(7)을 형성하고, 나머지 부분에는 고융점 금속이 그대로 남게 되는데, 이때 습식식각으로 고융점 금속을 제거한다.Then, as shown in b of FIG. 1, a high melting point metal 6 such as titanium is deposited on the front surface. After the heat treatment as shown in Figure 1c to react the high melting point metal (6) and silicon or polysilicon to form a silicide (7) on the gate and the source / drain, and the high melting point metal is left as it is, the wet Etching removes high melting point metals.
이러한 종래 기술의 실리사이드 형성방법에서는, 열처리 공정중에 소스/드레인 영역과 게이트 폴리실리콘에서 실리콘 원자가 고융점 금속을 통해 확산되어 실제로 산화막 사이드 월 스페이서 위까지 실리사이드가 형성되어, 결국 소스/드레인과 게이트간의 전기적 쇼트를 유발시킬 수 있다.In this prior art silicide formation method, silicon atoms in the source / drain regions and gate polysilicon diffuse through the high melting point metal during the heat treatment process, so that silicide is actually formed over the oxide sidewall spacers, resulting in electrical between source / drain and gate. May cause a short.
특히 게이트 폴리 단차가 낮거나, 스페이서 크기가 작으면 이 쇼트의 가능성이 더 커지게 된다.Especially if the gate poly step is low or the spacer size is small, the chance of this short becomes greater.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로서, 게이트 상의 실리사이드와 소스/드레인 상의 실리사이드을 분리시키기 위해서 산화막 사이드 월 스페이서를 높게 형성한다.The present invention is to solve this problem, to form a high oxide film side wall spacer to separate the silicide on the gate and the silicide on the source / drain.
이하 본 발명의 공정을 첨부도면 제 2 도를 참조하여 상술하면 다음과 같다.Hereinafter, the process of the present invention will be described in detail with reference to FIG. 2.
먼저 제 2 도의 a와 같이 실리콘 기판(11)에 필드 산화막을 형성한 후 게이트 산화막(12)을 성장시키고 게이트로 사용될 폴리실리콘(13) 및 질화막(14)을 차례로 중착시킨다. 그 후 포토/에치 공정을 거쳐 게이트 패터닝을 실시한다.First, a field oxide film is formed on the silicon substrate 11 as shown in FIG. 2A, the gate oxide film 12 is grown, and the polysilicon 13 and the nitride film 14 to be used as gates are sequentially stacked. Thereafter, gate patterning is performed through a photo / etch process.
이어서 제 2 도의 b와 같이, 산화막을 증착시킨 후 비등방성 건식식각으로 게이트 측벽에 사이드 월 스페이서(15)를 형성한다. 계속해서 질산 용액으로 게이트 폴리실리콘(13)상의 질화막(14)을 제거하고 티타늄(Ti)과 같은 고융점 금속(16)을 증착시킨다(제 2 도의 c). 그후 제 2 도의 d와 같이, 열처리하여 고융점 금속(16)과 실리콘 또는 폴리실리콘이 접촉하고 있는 게이트 폴리실리콘 위와 트랜지스터의 소스/드레인 위에만 실리사이드(17)를 형성하고, 습식식각하여 고융점 금속을 제거한다.Subsequently, as shown in b of FIG. 2, the sidewall spacers 15 are formed on the sidewalls of the gate by anisotropic dry etching after the oxide film is deposited. Subsequently, the nitride film 14 on the gate polysilicon 13 is removed with a nitric acid solution and a high melting point metal 16 such as titanium (Ti) is deposited (c in FIG. 2). Thereafter, as shown in FIG. 2D, heat treatment is performed to form silicide 17 only on the gate polysilicon where the high melting point metal 16 is in contact with silicon or polysilicon and on the source / drain of the transistor, and wet etching to form a high melting point metal. Remove it.
이와 같이 실리사이드를 형성하고, 사이드 월 스페이서를 게이트 위로 돌출시켜서 게이트 폴리실리콘 표면과 소스/드레인 표면간이 유효거리를 멀리하게 되고 따라서 게이트와 소스/드레인간의 전기적 쇼트를 억제한다.Thus, silicide is formed and the sidewall spacers are projected over the gate, so that the effective distance between the gate polysilicon surface and the source / drain surface is farther away, thereby suppressing electrical short between the gate and the source / drain.
본 발명의 다른 실시예가 제 3 도에 도시되어 있다. 본 실시예인 제 3 도의 a, b 및 c까지는 본 발명의 제 2 도의 a, b 및 c와 동일하게 진행시킨다.Another embodiment of the invention is shown in FIG. The steps up to a, b and c in FIG. 3 which are the present embodiment proceed in the same manner as a, b and c in FIG. 2 of the present invention.
계속해서 제 3 도의 d와 같이, 포토 레지스트(18)를 두껍게 스핀 코팅한 후 게이트 측벽에 형성된 사이드 월 스페이서(15) 상부가 포토 레지스트 위로 돌출되도록 에치백하여 표면을 평탄화시킨다. 그후 제 3 도의 e와 같이 포토 레지스트 위로 돌출된 고융점 금속 및 산화막 사이드 월 스페이서를 차례로 식각한다.Subsequently, as shown in FIG. 3D, the photoresist 18 is spin-coated thickly, and then the surface of the sidewall spacer 15 formed on the gate sidewall is etched back to protrude over the photoresist. Thereafter, as shown in FIG. 3E, the high melting point metal and the oxide side wall spacer protruding over the photoresist are sequentially etched.
마지막으로 제 3 도의 f와 같이, 포토 레지스트(18)를 제거하고 실리사이드(17)를 형성하기 의한 열처리를 실시하며, 고융점 금속을 제거하므로 게이트 폴리실리콘 위와 소소/드레인 영역에만 실리사이드가 형성되게 한다.Finally, as shown in f of FIG. 3, the heat treatment is performed by removing the photoresist 18 and forming the silicide 17, and removing the high melting point metal so that silicide is formed only on the gate polysilicon and only in the soso / drain regions. .
이와 같은 본 발명의 다른 실시예를 통해서, 사이드 월 스페이서 상단 부위의 고융점 금속을 제거하므로, 실리콘 확산경로를 차단시켜 게이트와 소스/드레인간의 쇼트를 방지할 수 있다.According to another embodiment of the present invention, since the high melting point metal of the upper portion of the sidewall spacer is removed, the silicon diffusion path may be blocked to prevent short between the gate and the source / drain.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023298A KR940007459B1 (en) | 1991-12-18 | 1991-12-18 | Forming method of silicide using self-align technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023298A KR940007459B1 (en) | 1991-12-18 | 1991-12-18 | Forming method of silicide using self-align technique |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930014890A KR930014890A (en) | 1993-07-23 |
| KR940007459B1 true KR940007459B1 (en) | 1994-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910023298A KR940007459B1 (en) | 1991-12-18 | 1991-12-18 | Forming method of silicide using self-align technique |
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| KR100605511B1 (en) * | 2004-09-21 | 2006-07-28 | 삼성전자주식회사 | Methods of forming at least one metal gate pattern in a semiconductor device |
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| KR930014890A (en) | 1993-07-23 |
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