KR0161842B1 - Method of forming transistor - Google Patents
Method of forming transistor Download PDFInfo
- Publication number
- KR0161842B1 KR0161842B1 KR1019900021631A KR900021631A KR0161842B1 KR 0161842 B1 KR0161842 B1 KR 0161842B1 KR 1019900021631 A KR1019900021631 A KR 1019900021631A KR 900021631 A KR900021631 A KR 900021631A KR 0161842 B1 KR0161842 B1 KR 0161842B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- gate
- silicide
- depositing
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract 5
- 238000005530 etching Methods 0.000 claims abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 28
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트 표면 저항을 감소시키고 RC시간지연을 감소시킬 수 있는 트랜지스터 제조방법을 제공하기 위한 것으로 이를 위하여 게이트용 산화막과 폴리실리콘막을 차례로 증착하고 이 게이트용 폴리실리콘막위에 Ti실리사이드막을 LPCVD법으로 증착하는 단계,The present invention is to provide a method for manufacturing a transistor which can reduce the gate surface resistance and reduce the RC time delay. Depositing,
포토공정을 실시하여 상기 Ti실리사이드위에 게이트 마스크를 형성하고 에치공정을 실시하여 게이트를 형성하는 단계,Performing a photo process to form a gate mask on the Ti silicide and performing an etch process to form a gate;
산화막을 형성하고 RIE방법으로 에치를 실시하여 측벽스페이서를 형성하는 단계,Forming an oxide film and etching it by a RIE method to form a sidewall spacer,
상기 Ti실리사이드위에 Ti막을 증착하고 어닐링을 실시하여 Ti실리사이드를 적정두께가 되도록 더 두껍게 형성하는 단계,Depositing a Ti film on the Ti silicide and performing annealing to form a thicker Ti silicide so as to have an appropriate thickness;
상기 게이트 마스크를 다시 사용하여 게이트상의 실리사이드화 되지 않은 상기 Ti막을 에천트로 제거하는 단계가 차례로 포함된다.Re-using the gate mask in turn removes the unsilicided Ti film on the gate with an etchant.
Description
제1도는 종래의 제조 공정단면도.1 is a cross-sectional view of a conventional manufacturing process.
제2도는 본 발명의 제조 공정단면도.2 is a cross-sectional view of the production process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 산화막1 substrate 2 oxide film
3 : 폴리실리콘막 4, 4a : Ti실리사이드막3: polysilicon film 4, 4a: Ti silicide film
5 : 게이트측벽스페이서 6 : Ti막5 gate side wall spacer 6 Ti film
본 발명은 트랜지스터 제조방법에 관한 것으로, 특히 Ti실리사이드(Salicide : Self-aligned Silicide)구조의 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a transistor, and more particularly, to a method for manufacturing a transistor having a Ti silicide (Salicide: Self-aligned Silicide) structure.
종래의 트랜지스터 제조공정을 첨부된 제1도 (a) 내지 제1도 (c)를 참조하여 상술하면 다음과 같다.A conventional transistor manufacturing process will be described below with reference to FIGS. 1A to 1C.
먼저 제1도 (a)와 같이 기판(10)위에 게이트용산화막(11)과 게이트용폴리실리콘막(12)을 차례로 형성한 다음 Ti막 자기정렬(Self-align)을 위해 포토/에치 공정을 거쳐 상기 게이트용 산화막(11)과 폴리실리콘막(12)의 불필요한 부분을 제거한다.First, as shown in FIG. 1A, a gate oxide film 11 and a gate polysilicon film 12 are sequentially formed on the substrate 10, and then a photo / etch process is performed to self-align the Ti film. The unnecessary portions of the gate oxide film 11 and the polysilicon film 12 are removed.
그리고 산화막을 증착하고 이를 RIE(Reactive Ion Etching) 방법으로 건식 에치(Etch)하여 게이트측벽스페이서(13)를 형성한다.The oxide film is deposited and dry etched using a reactive ion etching (RIE) method to form the gate sidewall spacers 13.
이어 제1도 (b)와 같이 전체적으로 Ti막(14)을 증착시킨다음 어닐링(Annealing)을 실시하여 제1도 (c)와 같이 상기 폴리실리콘막(12)의 표면에 Ti실리사이드막(15)을 형성한다.Subsequently, the Ti film 14 is entirely deposited as shown in FIG. 1 (b), followed by annealing to form the Ti silicide film 15 on the surface of the polysilicon film 12 as shown in FIG. To form.
그리고 Ti실리사이드막(15) 이외의 부분을 포토/에치 공정을 실시하여 제거하므로써 공정이 완료된다.The process is completed by removing a portion other than the Ti silicide film 15 by performing a photo / etch process.
그러나 상기 종래기술은 다음과 같은 단점이 있었다.However, the prior art has the following disadvantages.
콘택트 실리사이드의 경우 얇은막으로도 콘택트 저항을 감소시키며 접합에 데미지(Damage)를 입히지 않으나 종래기술은 어닐링 공정에 의해 폴리실리콘막위에 Ti실리사이드막이 형성되어 두께가 너무 얇으므로 RC지연시간 측면에서 뚜렷한 향상을 기대하기가 어렵다.In the case of contact silicide, even a thin film reduces contact resistance and does not cause damage to the junction. However, in the prior art, since the Ti silicide film is formed on the polysilicon film by an annealing process, the thickness is too thin. It's hard to expect.
본 발명은 상기 단점을 제거키위한 것으로 이를 첨부된 제2도 (a) 내지 제2도 (c)를 참조하여 상술하면 다음과 같다.The present invention is to eliminate the above disadvantages and will be described in detail with reference to the accompanying drawings 2 (a) to 2 (c) as follows.
먼저 제2도 (a)와 같이 기판(1)위에 게이트용 산화막(2)과 게이트용 폴리실리콘막(3) 및 Ti실리사이드막(4)을 LPCVD법으로 차례로 형성한 다음 포토 공정을 거쳐 게이트 마스크를 형성하고 건식 에치공정을 거쳐 상기 산화막(2)과 폴리실리콘막(3) 및 Ti실리사이드막(4)의 불필요한 부분을 제거한다. 그리고 산화막을 형성하고 이를 RIE방법으로 에치하여 게이트측벽스페이서(5)를 형성한다.First, as shown in FIG. 2A, a gate oxide film 2, a gate polysilicon film 3, and a Ti silicide film 4 are sequentially formed on the substrate 1 by LPCVD, followed by a gate mask through a photo process. And unnecessary portions of the oxide film (2), the polysilicon film (3) and the Ti silicide film (4) by a dry etching process. Then, an oxide film is formed and etched by the RIE method to form the gate side wall spacer 5.
이어 제2도 (b)와 같이 전체적으로 Ti막(6)을 증착시킨다음 어닐링을 실시하여 상기 Ti실리사이드막(4)보다 더 두꺼운 Ti실리사이드막(4a)을 형성한다.Subsequently, as shown in FIG. 2 (b), the Ti film 6 is entirely deposited and then annealed to form a Ti silicide film 4a thicker than the Ti silicide film 4.
그리고 게이트상의 실리사이드화 되지않은 Ti막(6)을 게이트마스크를 그대로 이용하여 에천트(Etchant)로 제거하므로써 공정이 완료된다.The process is completed by removing the silicided Ti film 6 on the gate with an etchant using the gate mask as it is.
이상과 같이 본 발명에 의하면 게이트상에 적정두께를 갖는 Ti실리사이드막이 형성되므로 게이트 저항 및 RC 지연시간을 감소시켜 줄 수 있다.As described above, according to the present invention, since the Ti silicide film having the appropriate thickness is formed on the gate, the gate resistance and the RC delay time can be reduced.
또한 게이트마스크를 그대로 활용하므로써 자기 정렬의 장점은 그대로 유지할 수 있게 된다.By using the gate mask as it is, the advantages of self-alignment can be maintained.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900021631A KR0161842B1 (en) | 1990-12-24 | 1990-12-24 | Method of forming transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900021631A KR0161842B1 (en) | 1990-12-24 | 1990-12-24 | Method of forming transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920011436A KR920011436A (en) | 1992-07-24 |
| KR0161842B1 true KR0161842B1 (en) | 1999-02-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900021631A KR0161842B1 (en) | 1990-12-24 | 1990-12-24 | Method of forming transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0161842B1 (en) |
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1990
- 1990-12-24 KR KR1019900021631A patent/KR0161842B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920011436A (en) | 1992-07-24 |
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