KR930008496B1 - Manufacturing method of lightly doped drain device - Google Patents
Manufacturing method of lightly doped drain device Download PDFInfo
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- KR930008496B1 KR930008496B1 KR1019900018292A KR900018292A KR930008496B1 KR 930008496 B1 KR930008496 B1 KR 930008496B1 KR 1019900018292 A KR1019900018292 A KR 1019900018292A KR 900018292 A KR900018292 A KR 900018292A KR 930008496 B1 KR930008496 B1 KR 930008496B1
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- oxide film
- polysilicon layer
- doped
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- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000011065 in-situ storage Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제 1a-f 도는 종래의 반도체 소자 제조공정도.1a-f is a conventional semiconductor device manufacturing process diagram.
제 2a-j 도는 본 발명에 따른 LDD소자 제조공정도.2a-j is a manufacturing process of the LDD device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : 필드산화막11 silicon substrate 12 field oxide film
13 : 버퍼산화막 15 : 포토레지스트13 buffer oxide film 15 photoresist
17 : 도우프드 폴리실리콘 21 : 게이트 산화막17: doped polysilicon 21: gate oxide film
22 : 게이트 24 : BPSG22: gate 24: BPSG
25 : 금속 19 : N＋소오스/드레인 영역25 metal 19 N + source / drain region
14 : 질화막 16 : 언도우프드 비정질 폴리실리콘14 nitride layer 16 undoped amorphous polysilicon
20 : 인시투 도우프드 폴리실리콘 20' : 사이드월20: in situ doped polysilicon 20 ': sidewall
본 발명은 자동 도우핑(Auto doping)에 대한 LDP(Lightly Doped Drain) 구조를 갖는 소자의 제조방법에 관한 것으로, 특히 N＋소오스/드레인 영역과 N-소오스/드레인 영역을 이온주입(implant)방법으로 형성하지 않고 폴리실리콘으로부터 불순물이 실리콘(Si) 쪽으로 도우핑되도록 한 LDD 소자 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a device having an LDP (Lightly Doped Drain) structure for automatic doping, in particular the N + source / drain region and the N-source / drain region as an ion implantation method (implant) The present invention relates to a method for manufacturing an LDD device in which impurities are doped from polysilicon to silicon (Si) without being formed.
종래의 반도체 소자의 제조에 있어서 자동도핑에 의해 소오스/드레인 영역을 형성하는 방법을 제 1a-f 도를 참조하여 상세히 설명하면 다음과 같다.A method of forming source / drain regions by automatic doping in the manufacture of a conventional semiconductor device will be described in detail with reference to FIGS. 1A-F.
먼저 제 1a 도에서와 같이 실리콘기판(1)위에 필드산화 공정에 의해 필드산화막(2)을 형성한 후, 버퍼산화막(3) 및 도우프드(Doped) 폴리실리콘(4)을 차례로 증착한다.First, as shown in FIG. 1A, the field oxide film 2 is formed on the silicon substrate 1 by a field oxidation process, and then the buffer oxide film 3 and the doped polysilicon 4 are sequentially deposited.
그 다음 제 1b 도에서와 같이 포토레지스트(5)를 도포하고 소정 패런으로 패터닝한 다음, 이 포토레지스트 패턴을 마스크로 하여 상기 도우프드 폴리실리콘(4)및 버퍼산화막(3)를 식각한 후, 제 1c 도에서와 같이 N＋소오스/드레인을 실리콘기판(1)에 형성시키기 위한 결과물 전면에 도우프드 폴리실리콘(6)을 증착시킨다.Then, as shown in FIG. 1B, the photoresist 5 is applied and patterned into a predetermined pattern, and then the doped polysilicon 4 and the buffer oxide film 3 are etched using the photoresist pattern as a mask. As shown in FIG. 1C, doped polysilicon 6 is deposited on the entire surface of the resultant to form N + source / drain on the silicon substrate 1.
그 다음 제 1d 도에서와 같이 도우프드 폴리실리콘(6)을 이방성 식각하여 상기 산화막(3)과 도우프드 폴리실리콘(4)의 측면에 사이드월(6')을 형성한 후, 문턱전압조절을 위한 VT이온주입을 실시한다.Then, as shown in FIG. 1d, the doped polysilicon 6 is anisotropically etched to form sidewalls 6 'on the side of the oxide film 3 and the doped polysilicon 4, and then the threshold voltage adjustment is performed. V T ion implantation is performed.
그다음 제 1e 도에서와 같이 결과물 전면에 게이트 산화막(7)과 게이트 폴리실리콘(8)을 증착한 다음 게이트(8)를 디파인(define)하게 되면 상기 도우프드 폴리실리콘(6)으로부터 실리콘기판쪽으로 불순물이 도우핑되어 실리콘기판(1)에 N＋소오스/드레인영역(10a)이 형성되며,그 후 제 1f 도에서와 같이 BPSG(9)를 증착하고 콘택홀(Contact hole)을 개방한 후 금속(10)을 증착하고 패터닝한다.Then, as shown in FIG. 1E, the gate oxide film 7 and the gate polysilicon 8 are deposited on the entire surface of the resultant, and then the gate 8 is defined as fine impurities from the doped polysilicon 6 toward the silicon substrate. This is doped to form an N + source / drain region 10a in the silicon substrate 1, and then, as shown in FIG. 1f, the BPSG 9 is deposited and the contact hole is opened, and then the metal 10 ) Is deposited and patterned.
그런데 상기와 같은 종래의 반도체 소자 제조공정에서는 N＋소오스/드레인영역을 자동 도우핑시킬 수 있으나 N-소오스/드레인의 영역은 구성할 수 없는 통상적인 디바이스(Conventional Device) 구조이므로 쇼트채널로 갈수록 핫(hot) 캐리어 때문에 소자의 파괴(degradation)를 초래할 수 있는 단점이 있었다.However, in the conventional semiconductor device manufacturing process as described above, the N + source / drain region can be automatically doped, but the N-source / drain region cannot be configured. Hot carriers have the disadvantage of causing device degradation.
본 발명은 이러한 단점을 해결하기 위해 안출된 것으로, 첨부도면을 참조하여 상세히 설명하면 다음과 같다.The present invention has been made to solve these disadvantages, and will be described in detail with reference to the accompanying drawings.
먼저 제 2a 도에서와 같이 실리콘기판(11)상에 필드산화 공정을 통해 소정영역에 필드산화막(12)을 형성하고 채널스톱 이온주입을 실시한 후, 결과물 전면에 버퍼 산화막(13)과 , 질화막(14)을 증착한다.First, as shown in FIG. 2A, the field oxide film 12 is formed on a predetermined region on the silicon substrate 11 through a field oxidation process, and channel stop ion implantation is performed. Then, the buffer oxide film 13 and the nitride film ( 14) is deposited.
그 다음 제 2b 도에서와 같이 포토레지스트로 된 채널영역 마스크(15)를 이용하여 상기 질화막(14)을 식각한 후 포토레지스트 패턴을 제거한다.'Next, as shown in FIG. 2B, the nitride layer 14 is etched using the channel region mask 15 made of photoresist, and then the photoresist pattern is removed.
그리고 제 2c 도에서와 같이 상기 버퍼산화막(13)을 습식식각(wet etch) 법으로 식각한 후 제 2d 도에서와 같이 상기 질화막을 제거한 다음 결과물 전면에 언도우프드폴리실리콘(16)을 증착하고 그 후 제 2e 도에서와 같이 N+소오스/드레인을 형성하기 위해 상기 언도우프드 폴리실리콘층(16)에 As를 이온주입하여 도우프드 폴리실리콘(17)으로 만든다.Then, as shown in FIG. 2c, the buffer oxide film 13 is etched by wet etching, and then, as shown in FIG. 2d, the nitride film is removed, and then the undoped polysilicon 16 is deposited on the entire surface. Thereafter, As is ion-implanted into the undoped polysilicon layer 16 to form N + source / drain as shown in FIG. 2E to form the doped polysilicon 17.
그 다음 제 2c 도에서와 같이 N+소오스/드레인영역을 한정하는 포토레지스트패턴(18)을 이용하여 상기 As이온이 주입된 폴리실리콘(17a)를 식각한 후, 제 2g 도에서와 같이 어닐링(annnealling) 공정을 행하면 상기As이온이 주입된 폴리시리콘층(17a)으로부터 불순물이 기판으로 도핑되어 N+소오스/드레인영역(19)이 실리콘기판(1)에 형성된다.Next, as shown in FIG. 2C, the As ion-implanted polysilicon 17a is etched using the photoresist pattern 18 defining the N + source / drain region, and then annealed as shown in FIG. 2G. ) Process, impurities are doped into the substrate from the polysilicon layer 17a into which the As ions are implanted, and an N + source / drain region 19 is formed on the silicon substrate 1.
그 다음 제 2h 도에서와 같이 N+소오스/드레인을 형성시키기 위해 인-시투(In-situ) 도우프트 폴리실리콘(20)을 결과물 전면에 증착시민 후 제 2i 도에서와 같이 상기 인-시투 도우프드 폴리실리콘(20)을 이방성 식각하여 사이드월(20')을 형성하고 VT이온주입을 실시한 다음, 결과물 전면에 게이트산화막(21) 및 게이트 폴리실리콘(22)을 차례로 증착시킨 후 패터닝하여 게이트(22)를 형성한다.In-situ doped polysilicon 20 is then deposited on the entire surface of the resultant to form N + source / drain as shown in Figure 2h and then the in-situ doped as shown in Figure 2i. to form a poly-silicon (20) side wall (20 ') by anisotropic etching and patterning was subjected to V T ion implantation, and then, sequentially depositing a gate oxide film 21 and the gate polysilicon 22, the resulting front gate ( 22).
이때 게이트 산화막(21)이 형성 공정시의 열처리로 인해 상기 인-시투 도우프드 폴리실리콘으로 된 사이드월(20')로부터 불순물이 기판으로 도핑되어 N-소오스/드레인영역(LDD 영역)(23)이 자동적으로 형성된다.At this time, an impurity is doped into the substrate from the sidewall 20 'made of the in-situ doped polysilicon due to the heat treatment during the formation process of the gate oxide film 21 to form the N-source / drain region (LDD region) 23. This is formed automatically.
이때, 상기 인-시투 도우프드 폴리실리콘(20)을 이방성 식각하여 사이드월(20')을 형성할때 실리콘기판의 채널부위를 어느 정도 식각하여 N-소오스/드레인영역(23)의 가장자리 부분을 보다 얕게 형성할 수도 있다.(제 2i 도 A 참조).At this time, when the in-situ doped polysilicon 20 is anisotropically etched to form the sidewall 20 ', the channel portion of the silicon substrate is etched to some extent so that the edge portion of the N-source / drain region 23 is removed. It can also form shallower. (See FIG. 2i FIG. A).
그리고 나서 제 2j 도에서와 같이 결과물 전면에 BPSG(24)를 증착하고 콘택홀을 개방한 후, 금속(25)의 증착 및 패터닝 공정을 행함으로써 공정을 완료한다.Then, as shown in FIG. 2j, the BPSG 24 is deposited on the entire surface of the resultant product, the contact hole is opened, and the deposition and patterning process of the metal 25 is performed to complete the process.
즉, 본 발명은 인-시투 도우프드 폴리실리콘을 사용하여 단수화된 공정에 의해 N-소오스/드레인의 영역을 자동 도우핑시켜 형설할 수 있다.That is, the present invention can be formed by automatically doping the regions of the N-source / drain by a singularized process using in-situ doped polysilicon.
따라서 핫 캐리어에 의한 소자의 파괴(degradation)를 개선시킬 수 있다.Therefore, the degradation of the device by the hot carrier can be improved.
또한 상기한 바와같이 N-소오스/드레인 영역을 형성시키기 위해 폴리실리콘을 이방성 식각하므로써 채널(channel)쪽의 실리콘을 식각하므로 N-소오스/드레인의 가장자리 부분이 얕게(Shallow)되는 효과를 얻을 수 있다.In addition, as described above, the silicon on the channel side is etched by anisotropically etching polysilicon to form the N-source / drain region, so that an edge portion of the N-source / drain may be shallow. .
또한, 자동 도우핑으로 소오스/드레인 영역을 먼저 형성시키고 게이트를 형성시키므로 대칭적인 소자를 제작할 수 있으며 N-소오스/드레인과 N-소오스/드레인이 게이트에 오버랩(over lap) 되므로 핫 캐리어 효과도 더우 개선된다.In addition, the source / drain regions are first formed by automatic doping and the gate is formed to form a symmetrical device. Since the N-source / drain and the N-source / drain overlap the gates, the hot carrier effect is further increased. Is improved.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900018292A KR930008496B1 (en) | 1990-11-13 | 1990-11-13 | Manufacturing method of lightly doped drain device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019900018292A KR930008496B1 (en) | 1990-11-13 | 1990-11-13 | Manufacturing method of lightly doped drain device |
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| KR920010771A KR920010771A (en) | 1992-06-27 |
| KR930008496B1 true KR930008496B1 (en) | 1993-09-07 |
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| KR1019900018292A KR930008496B1 (en) | 1990-11-13 | 1990-11-13 | Manufacturing method of lightly doped drain device |
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