KR930003688Y1 - Horizontal and vertical sync-signal interface circuit - Google Patents

Abstract

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Description

Horizontal and vertical sync signal interface circuit

1 is a detailed view showing an embodiment of the interface circuit of the present invention.

2 is a truth table of the parts of FIG. 1 according to the mode.

* Explanation of symbols for main parts of the drawings

10: horizontal and vertical synchronous signal processing unit 11, 12: integrator

20: VGA mode determination unit 21,22: retriggerable mono multi

30: discrimination signal output unit 31, 32: decoder

EOR1-EOR4: Exclusive Oagate HS: Horizontal Sync Signal

VS: Vertical Sync Signal : 1st-3rd VGA mode determination signal

: Super VGA mode discrimination signal : IBM 8514A mode determination signal

The present invention relates to a horizontal and vertical synchronous signal interface circuit for interfacing vertical and horizontal synchronous signals input to a monitor.

The number of fonts of the image displayed on the monitor differs depending on the VGA mode, the super VGA mode, and the IBM 8514A mode. That is, 640 × 350, 640 × 400 and 640 × 480 in the VGA mode, 800 × 600 in the super VGA mode, and 1024 × 768 in the IBM 8514A mode. In addition to the number of fonts, the polarity and frequency of the horizontal and vertical sync signals are also different.

Therefore, in a multi-mode monitor in which one monitor is operated in several modes, the polarity of the horizontal and vertical synchronization signals needs to be converted to be suitable for the monitor, and an interface circuit for determining each mode and informing it is required.

There have been various conventional interface circuits having such a function. However, these interface circuits have a problem in that the circuit configuration is very complicated, and it is very expensive to use an integrated device dedicated to the interface, which causes a lot of economic burden on the user.

Accordingly, an object of the present invention is to provide an interface circuit having a simple configuration for determining each mode as well as converting the polarity of the horizontal and vertical synchronous signals to a monitor using a general-purpose integrated device.

The present invention having this purpose uses the frequency of the horizontal synchronizing signal and the polarity of the horizontal and vertical synchronizing signal to determine the polarity of the horizontal and vertical synchronizing signal and to convert the polarity of the horizontal and vertical synchronizing signal appropriately for the monitor. A vertical mode signal processing unit, a VGA mode determining unit which determines whether the mode is a VGA mode by the frequency of the horizontal synchronizing signal output from the horizontal and vertical synchronizing signal processing unit, and a polarity discrimination signal and the VGA mode discrimination unit of the horizontal and vertical synchronizing signal processing unit And a discrimination signal output unit for outputting a first to third VGA mode, a super VGA mode, and an IBM 8514A mode discrimination signal as a negative discrimination signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the interface circuit of the present invention.

1 is a detailed view showing an embodiment of the interface circuit of the present invention, as shown in the present invention, the present invention is to determine the polarity of the horizontal synchronization signal (HS) and vertical synchronization signal (VS) and to convert to positive polarity A horizontal and vertical synchronous signal processing unit 10 to output, a VGA mode determination unit 20 for determining whether the VGA mode is a frequency of a horizontal synchronous signal output by the horizontal and vertical synchronous signal processing unit 10, and the horizontal and As the polarity discrimination signal output from the vertical synchronization signal processing unit 10 and the discrimination signal of the VGA mode discrimination unit 20, the first to third VGA mode discrimination signals ( ), Shoe VGA mode discrimination signal And IBM 8514A mode determination signals It is composed of a determination signal output unit 30 for outputting.

In the horizontal and vertical synchronous signal processing unit 10, the horizontal and vertical synchronous signals HS and VS are input to one side of the resistors R1, R2, and the exclusive OA gates EOR1, EOR3, EOR2, and EOR4. The other input terminal of the exclusive orifice (EOR1) or (EOR2) is grounded, and the output terminals of the exclusive oragate (EOR1, EOR2) are resistors (R3) (R4) and capacitor (C1). (C2) is connected to the input terminals of the integrators (11) and (12) to output the polarity discrimination signal to the output terminals (A) and (B) of the integrators (11) and (12). (B) is connected to the other input terminal of the exclusive orifice (EOR3, EOR4), so that the output signal of the exclusive oragate (EOR3) is connected in parallel to the capacitor (C3) (C4) and the resistor (R5) ( R6) is output as a horizontal synchronous signal and a clamp signal, and the output signal of the exclusive oragate EOR4 is output as a vertical synchronous signal through the condenser C5.

The VGA mode determining unit 20 is a retriggerable monomulti connected to an output terminal of the exclusive oragate EOR3, to which a time constant circuit of a resistor R7, a variable resistor VR, and a capacitor C7 is connected. The retriggerable monomulti 22 in which the time terminal circuit of the resistor R8 and the capacitor C8 is connected to the output terminal Q1 of the retriggerable monomulti 21 by connecting to the trigger terminal T1 of the terminal 21). Is connected to the trigger terminal T2 of the output terminal Q2 of the retriggerable mono Is connected to the cathodes of the constant voltage diodes ZD2 and ZD3 via resistors R9 and R10.

The determination signal output section 30 connects the connection points of the resistors R9, R10 and the constant voltage diodes ZD2, ZD3 to the enable ends EN1, EN2 of the decoders 31, 32, The output terminals A and B of the integrators 11 and 12 are connected to the input terminals D11 and D21 (D12 and D22) of the decoders 31 and 32, and the outputs of the decoders 31 and 32 are connected. A first to third VGA mode discrimination signal is connected to the anodes of the diodes D1-D3 by connecting the cathodes of the terminals D1-D3 (D4-D5). And the super VGA mode determination signal to the anode of the diodes D4 and D5. And IBM 8514A mode determination signals Is configured to output.

In the drawing description of FIG. 1, reference numeral Vcc denotes a power terminal to which an operating power is applied, ZD1 and C6 are power terminals to which an operating power is applied, and ZD1 and C6 are constant voltage diodes and capacitors for stabilizing the operating power.

The operation of the present invention configured as described above will be described by dividing each mode with reference to the truth table of FIG.

1. In case of 1VGA mode

In the case of the first VGA mode, as shown in FIG. 2, the horizontal and vertical synchronization signals HS and VS have frequencies of 31.5 KHz and 70 Hz, respectively, and polarities are positive and negative polarities, respectively.

When the horizontal and vertical synchronous signal HS (VS) of such a frequency is input, the input horizontal and vertical synchronous signal HS (VS) is inverted through the exclusive OR gate EOR1 (EOR2), and the integrator Since the integrators 11 and 12 output low and high potentials, the input terminals D11 and D21 (D12 and D22) and the exclusive ora of the decoders 31 and 32 are integrated. It is applied to the other input terminal of the gates EOR3 (EOR4).

Therefore, the horizontal synchronizing signal HS having positive polarity is output as a horizontal synchronizing signal and a clamp signal passing through the exclusive ora gate EOR3 with positive polarity as it is, and the vertical synchronizing signal VS having negative polarity is The positive polarity is converted and output through the exclusive oragate EOR4.

The positive horizontal synchronous signal output from the exclusive oragate EOR3 is applied as a trigger signal to the trigger terminal T1 of the retriggerable mono multi 21, where the frequency of the horizontal synchronous signal is 31.5 KHz. If only the time constants of the resistor R7, the variable resistor VR and the capacitor C7 are set so that the retriable monomulti 21 continues to be triggered, the retriggerable mono multi 21 outputs a pulse signal. Since the trigger signal is applied to the trigger terminal T2 of the retriggerable monomulti 22, the retriggerable mono multi 22 is continuously triggered, and the output terminal Q2 ( Are output to the enable terminals EN1 and EN2 of the decoders 31 and 32, respectively.

Therefore, since the decoder 31 is enabled, and the low potential and high potential output from the integrators 11 and 12 are decoded to output the low potential to the output terminal Q11, the first VGA mode discrimination signal having a low potential ( ) Is outputted to indicate the first VGA mode.

2. In case of 2VGA mode

In the case of the second VAG mode, as shown in FIG. 2, the horizontal and vertical synchronization signals HS (VS) have frequencies of 31.5 KHz and 70 Hz, respectively, as in the first VGA mode, and the polarities thereof are negative and positive polarities.

When such a horizontal and vertical synchronization signal HS (VS) is input, the input horizontal and vertical synchronization signal HS (VS) is inverted through the exclusive oragate EOR1 and EOR2, and the integrator 11 Since integrator 11 is integrated, the integrators 11 and 12 output high and low potentials, respectively.

Therefore, the horizontal synchronizing signal HS input with negative polarity is converted into positive polarity through the exclusive oragate EOR3 and then output as a horizontal synchronizing signal and a clamp signal, and the vertical synchronizing signal VS having positive polarity. Is output through the exclusive OA gate (EOR4).

In addition, since the horizontal synchronous signal of positive polarity output from the exclusive oragate EOR3 is applied as a trigger signal to the trigger terminal T1 of the retriggerable monomulti 21, the retriggerable mono multi 21 is a pulse signal. Output, and the retriggerable mono multi 22 is output terminal The high power and low potential are output to the enable terminals EN1 and EN2 of the decoders 31 and 32.

Therefore, since the decoder 31 is enabled, and the high potential and low potential output from the integrators 11 and 12 are decoded and the low potential is output to the output terminal Q12, the low voltage second VGA mode discrimination signal is generated. ( ) Is outputted to indicate the second VGA mode.

3. In the third VGA mode

In the third VGA mode, as shown in FIG. 2, the horizontal and vertical synchronization signals HS and VS are 31.5 KHz and 60 Hz, respectively, and the polarity is mode negative.

When such a horizontal and vertical synchronization signal HS (VS) is input, the input horizontal and vertical synchronization signal HS (VS) is inverted through the exclusive oragate EOR1 and EOR2, and the integrator 11 Since integrator 11 is integrated, both integrators 11 and 12 output high potentials.

Therefore, the horizontal and vertical synchronizing signals HS (VS) having negative polarity are converted into positive polarities through the exclusive oar gates EOR3 and EOR4 and output.

Since the horizontal synchronous signal of the positive polarity output from the exclusive oragate EOR3 is applied as a trigger signal to the trigger terminal T1 of the retriable monomulti 21, the retriggerable mono multi 21 is a pulse signal. Is output and the retriggerable mono multi 22 is output terminal ) And high potential and low potential are output to the enable terminals EN1 and EN2 of the decoders 31 and 32.

Therefore, the decoder 31 is enabled, and the low potential is output to the output terminal Q13 by decoding the high potential and the high potential output from the integrators 11 and 12, so that the low potential is converted into the third VGA mode discrimination signal. ( ) Is outputted to inform the third VGA mode.

4. Super VGA Mode In Super VGA mode, the frequencies of the Vagati horizontal and vertical synchronization signal (HS) VS shown in FIG. 2 are 35.2 KHz and 56 Hz, respectively, and both polarities are negative.

When such a horizontal and vertical synchronization signal HS (VS) is input, the input horizontal and vertical synchronization signal HS (VS) is inverted through the exclusive oragate EOR1 and EOR2, and the integrator 11 Since integrator 11 is integrated, both integrators 11 and 12 output high potentials.

Therefore, the horizontal and vertical synchronous signals HS (VS) having negative polarity are converted into positive polarities through the exclusive oragate EOR3 and EOR4 and output.

Since the horizontal synchronization signal of 35.2 KHz output from the exclusive oragate EOR3 is applied as a trigger signal to the trigger terminal T1 of the retriggerable monomulti 21, the retriggerable mono multi 21 is continued. Triggered to output a high potential to the output terminal (Q1), the retriggerable mono-multi-22 is not triggered, output terminal (Q2) ( Low potential and high potential are output to the enable stages EN1 and EN2 of the decoders 31 and 32.

Therefore, the decoder 32 is enabled and the low potential is output to the output terminal Q23 by decoding the high potentials output from the integrators 11 and 12, so that the super VGA mode discrimination signal of low potential ( ) Is displayed to indicate that it is a super VGA mode.

5. In IBM 8514A mode In IBM 8514A mode, the horizontal and vertical sync signal (HS) (VS) frequencies are 35.5KHz and 47Hz, respectively, as shown in Figure 2, and both polarities are positive.

Since the horizontal and vertical synchronization signals HS (VS) are inverted through the exclusive oar gates EOR1 and EOR2 and integrated in the integrators 11 and 12, the integrators 11 and 12 are both classical. Will print the above.

Therefore, the horizontal and vertical synchronization signals HS (VS) having the negative polarity are output while passing through the exclusive oragate EOR3 and EOR4 with the positive polarity as it is.

The horizontal sync signal of 35.2 KHz, which is output from the exclusive OR gate EOR3, is applied as a trigger signal to the trigger terminal T1 of the retriggerable monomulti 21, and thus the retriggerable mono multi 21. Continues to be triggered, and the high potential is continuously output to the output terminal Q1, so that the retriggerable monomultiplex 22 outputs the output terminal Q2 ( Outputs a low potential and a high potential, and is applied to the enable terminals EN1 and EN2 of the decoders 31 and 32.

Therefore, the decoder 32 is enabled, and the low potential IBM 8514A mode discrimination signal is decoded to the output terminal Q20 by decoding the low potential outputted from the integrators 11 and 12. ) To indicate that it is in IBM 8514A mode.

As described in detail above, the present invention uses only general-purpose integrated devices to convert the polarity of the horizontal and vertical synchronization signals appropriately for the monitor, as well as to discriminate the mode, thereby making the configuration simple and relatively inexpensive. There is an effect such as to reduce the economic burden on the user who needs a monitor.

Claims (3)

The horizontal and vertical synchronization signal processing unit 10 for determining the polarity of the input horizontal synchronization signal HS and the vertical synchronization signal VS and converting the polarity into a positive polarity and outputting the horizontal and vertical synchronization signal processing unit 10. VGA mode determination unit 20 for outputting a determination signal for determining whether the output mode is a VGA mode or other mode according to the frequency of the horizontal synchronization signal output from the and selectively according to the discrimination signal of the VGA mode determination unit 20 First and second decoders 31 and 32 are enabled, and the first to third VGA mode determination signals according to polarity discrimination signals output from the horizontal and vertical synchronization signal processing units 10 ), Super VGA mode discrimination signal ( ) And IBM 8514A mode determination signal ( Horizontal and vertical synchronous signal interface circuit, characterized in that consisting of a discrimination signal output unit 30 for outputting any one of. The horizontal and vertical synchronous signal processing unit 10 includes an exclusive oragate EOR1 (EOR2) for inverting the horizontal and vertical synchronous signals HS and VS, respectively, and the exclusive. Integrators 11 and 12 for integrating the output signals of the OR gates EOR1 and EOR2 and outputting the polarity discrimination signals of the horizontal and vertical synchronization signals HS and VS, and the horizontal and vertical synchronization signals HS. Exclusive OA gate (EOR3) (EOR4) which converts the polarity of horizontal and vertical synchronization signal (HS) (VS) into positive polarity as output signals of VS and integrators 11 and 12 Horizontal and vertical synchronous signal interface circuit, characterized in that. The method of claim 1, wherein the VGA mode determination unit 20 is retriggered to output a high potential when the VGA mode is not generated in the VGA mode according to the frequency of the horizontal synchronization signal HS. The retriggerable mono multi 21 and the retriggerable mono multi 21 are continuously retriggered when the pulse signal outputs a pulse signal and output a VGA mode discrimination signal 22. Horizontal and vertical synchronous signal interface circuit.