KR920704225A - Buslocking First-In, First-Out Multi-Processor Communication System - Google Patents

Buslocking First-In, First-Out Multi-Processor Communication System

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Publication number
KR920704225A
KR920704225A KR1019920701854A KR920701854A KR920704225A KR 920704225 A KR920704225 A KR 920704225A KR 1019920701854 A KR1019920701854 A KR 1019920701854A KR 920701854 A KR920701854 A KR 920701854A KR 920704225 A KR920704225 A KR 920704225A
Authority
KR
South Korea
Prior art keywords
message data
fifo
vme bus
processor
bus
Prior art date
Application number
KR1019920701854A
Other languages
Korean (ko)
Inventor
엠. 피츠 윌리엄
이. 블라이트맨 스테판
디. 스타 대릴
Original Assignee
원본미기재
오스펙스 시스템즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 원본미기재, 오스펙스 시스템즈, 인코포레이티드 filed Critical 원본미기재
Publication of KR920704225A publication Critical patent/KR920704225A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)

Abstract

내용 없음No content

Description

버스록킹 선입선출 멀티-프로세서 정보전달 시스템Buslocking First-In, First-Out Multi-Processor Communication System

[도면의 간단한 설명][Brief Description of Drawings]

제1도는 하드웨어가 본 발명을 지원하는 바람직한 실시예를 나타내 도면.1 illustrates a preferred embodiment in which hardware supports the present invention.

제2도는 VME버스에 요구되어지는 주요신호라인이 중요 기능 유니트의 데이타 전송버스에 연결된 것을 설명한 도면.2 is a view for explaining that the main signal lines required for the VME bus are connected to the data transfer bus of the critical function unit.

제3도는 VME버스 스탠다드에 요구되어지는 주요신호라인이 종속기능 유니트의 데이타 전송버스에 연결된 것을 설명하는 도면.3 is a view for explaining that the main signal line required for the VME bus standard is connected to the data transfer bus of the subordinate functional unit.

제12도는 본 발명에서 실현된 메시지 데이타전송을 보여주는 순서도, 제13도는 본 발명의 버스록킹 FIFO 멀티프로세서 데이타 전송 시스템의 도면.12 is a flow chart showing message data transmission realized in the present invention, and FIG. 13 is a diagram of a buslocking FIFO multiprocessor data transfer system of the present invention.

제14도는 본 발명인 버스록킹 FIFO 멀티프로세서 데이타전송 시스템에 관계된 한 프로에서 실현을 나타내는 도면.14 shows an implementation in one program relating to the present invention, the buslocking FIFO multiprocessor data transfer system.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (4)

마스터 프로세서에서 전송된 메시지 데이타를 받아들이고 저장하는 VME버스와 서로 연결되어 있고, 메시지 데이타를 저장할 수 없음을 나타내는 FIFO FULL 상태를 표시하며, FIFO FULL 상태의 존재를 지시하는 FIFO FULL 시그널을 발생하는 FIFO 수단과 상기 FIFO 수단에서 FIFO FULL 신호를 수신하여 응답하는 VME버스를 통해 버스 에러 신호를 전송하기 위한 VME버스와 FIFO 수단이 서로 연결된 수단으로 구성되는 VME버스를 통해 마스터 프로세서에서 슬레이브 프로세서로 메시지 데이타를 전송하는 메시지 전송 시스템.FIFO means connected to the VME bus that accepts and stores the transmitted message data from the master processor, displays a FIFO FULL status indicating that the message data cannot be stored, and generates a FIFO FULL signal indicating the presence of the FIFO FULL status. And a VME bus for transmitting a bus error signal through a VME bus which receives and responds to a FIFO FULL signal from the FIFO means, and transmits the message data from the master processor to the slave processor through a VME bus composed of means connected to each other. Message transmission system. 마스터 프로세서에서 전송된 메시지 데이타를 수신하고 VME버스와 상호 연결되어 있는 메시지 데이타 채널수단과 위 메시지 채널 장치와 연결된 메시지 데이타를 저장하고, 메시지 데이타를 저장할 수 없음을 나타내는 FIFO FULL 상태를 표시하며, 상기 FIFO FULL 상태의 존재를 지시하는 FIFO FULL 시그널을 발생하는 FIFO 수단과 상기 FIFO 수단에서 FIFO FULL 신호를 받아 응답하는 VME버스를 통해 버스에러 신호를 전송하는 수단으로 구성되는 VME버스를 통해 마스터 프로세서에서 슬레이브 프로세서로 메시지 데이타를 전송하는 메시지 전송 시스템.Receives the message data transmitted from the master processor and stores the message data channel means interconnected with the VME bus and the message data connected with the above message channel device, and displays a FIFO FULL state indicating that the message data cannot be stored. Slave from the master processor through the VME bus consisting of a FIFO means for generating a FIFO FULL signal indicating the presence of a FIFO FULL state and a means for transmitting a bus error signal through a VME bus that receives and responds to a FIFO FULL signal from the FIFO means. Message transfer system for sending message data to a processor. 슬레이브 프로세서와 서로 연결된 FIFO 수단에 VME버스를 통해 메시지 데이타를 저장하기 위해 라이트 사이클을 개시하는 단계와 전송 할 메시지 데이타를 FIFO 수단의 포착할 수 없음을 나타내기 위해 라이트 사이클 개시에 대한 응답으로 버스에러 신호를 보내는 단계로 이루어짐을 특징으로 하는 슬레이브 프로세서가 전송된 메시지 데이타를 저장할 수 없는 경우에 마스터 프로세서에서 슬레이브 프로세서로 VME버스를 통한 메시지 데이타의 전달을 중지시키는 방법.Initiating a write cycle to store message data over a VME bus to a FIFO means interconnected with a slave processor and a bus error in response to the start of the write cycle to indicate that the message data to be transmitted cannot be captured by the FIFO means. A method for stopping the transmission of message data over a VME bus from a master processor to a slave processor when the slave processor is unable to store the transmitted message data. 제3항에 있어서, 예정된 시간이 경과된 후에 라이트 사이클을 재개하는 부가적인 단계를 포함하는 것을 특징으로 하는 메시지 데이타의 전달을 중지시키는 방법.4. The method of claim 3 including the additional step of resuming a write cycle after a predetermined time has elapsed. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019920701854A 1990-02-02 1990-08-20 Buslocking First-In, First-Out Multi-Processor Communication System KR920704225A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47435090A 1990-02-02 1990-02-02
US474,350 1990-02-02
PCT/US1990/004697 WO1991011768A1 (en) 1990-02-02 1990-08-20 Bus locking fifo multi-processor communication system

Publications (1)

Publication Number Publication Date
KR920704225A true KR920704225A (en) 1992-12-19

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KR1019920701854A KR920704225A (en) 1990-02-02 1990-08-20 Buslocking First-In, First-Out Multi-Processor Communication System

Country Status (7)

Country Link
EP (1) EP0512993A4 (en)
JP (1) JPH05505478A (en)
KR (1) KR920704225A (en)
AU (2) AU6431990A (en)
CA (1) CA2074530A1 (en)
IL (1) IL95448A0 (en)
WO (1) WO1991011768A1 (en)

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* Cited by examiner, † Cited by third party
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US6792513B2 (en) 1999-12-29 2004-09-14 The Johns Hopkins University System, method, and computer program product for high speed backplane messaging
WO2001048620A1 (en) * 1999-12-29 2001-07-05 The Johns Hopkins University System, method, and computer program product for high speed backplane messaging
US7457822B1 (en) 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247638A (en) * 1975-10-15 1977-04-15 Toshiba Corp Information processing device
US4285038A (en) * 1976-10-15 1981-08-18 Tokyo Shibaura Electric Co., Ltd. Information transfer control system
EP0064818A1 (en) * 1981-04-20 1982-11-17 Pitney Bowes, Inc. Data collision avoidance method
US4423482A (en) * 1981-06-01 1983-12-27 Sperry Corporation FIFO Register with independent clocking means

Also Published As

Publication number Publication date
EP0512993A4 (en) 1993-02-24
EP0512993A1 (en) 1992-11-19
JPH05505478A (en) 1993-08-12
AU6431990A (en) 1991-08-21
WO1991011768A1 (en) 1991-08-08
IL95448A0 (en) 1991-06-30
CA2074530A1 (en) 1991-08-03
AU7435294A (en) 1994-12-15

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