AU7435294A - Bus locking FIFO multi-processor communication system - Google Patents

Bus locking FIFO multi-processor communication system

Info

Publication number
AU7435294A
AU7435294A AU74352/94A AU7435294A AU7435294A AU 7435294 A AU7435294 A AU 7435294A AU 74352/94 A AU74352/94 A AU 74352/94A AU 7435294 A AU7435294 A AU 7435294A AU 7435294 A AU7435294 A AU 7435294A
Authority
AU
Australia
Prior art keywords
communication system
processor communication
bus locking
fifo multi
locking fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU74352/94A
Inventor
Stephen E. Blightman
William M. Pitts
Darryl D. Starr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Auspex Systems Inc
Original Assignee
Auspex Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Auspex Systems Inc filed Critical Auspex Systems Inc
Publication of AU7435294A publication Critical patent/AU7435294A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Tests Of Electric Status Of Batteries (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)
AU74352/94A 1990-02-02 1994-09-30 Bus locking FIFO multi-processor communication system Abandoned AU7435294A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47435090A 1990-02-02 1990-02-02
US474350 1990-02-02

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
AU64319/90A Division AU6431990A (en) 1990-02-02 1990-08-20 Bus locking fifo multi-processor communication system

Publications (1)

Publication Number Publication Date
AU7435294A true AU7435294A (en) 1994-12-15

Family

ID=23883131

Family Applications (2)

Application Number Title Priority Date Filing Date
AU64319/90A Abandoned AU6431990A (en) 1990-02-02 1990-08-20 Bus locking fifo multi-processor communication system
AU74352/94A Abandoned AU7435294A (en) 1990-02-02 1994-09-30 Bus locking FIFO multi-processor communication system

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU64319/90A Abandoned AU6431990A (en) 1990-02-02 1990-08-20 Bus locking fifo multi-processor communication system

Country Status (7)

Country Link
EP (1) EP0512993A4 (en)
JP (1) JPH05505478A (en)
KR (1) KR920704225A (en)
AU (2) AU6431990A (en)
CA (1) CA2074530A1 (en)
IL (1) IL95448A0 (en)
WO (1) WO1991011768A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2603901A (en) * 1999-12-29 2001-07-09 Johns Hopkins University, The System, method, and computer program product for high speed backplane messaging
US6792513B2 (en) 1999-12-29 2004-09-14 The Johns Hopkins University System, method, and computer program product for high speed backplane messaging
US7457822B1 (en) 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247638A (en) * 1975-10-15 1977-04-15 Toshiba Corp Information processing device
US4285038A (en) * 1976-10-15 1981-08-18 Tokyo Shibaura Electric Co., Ltd. Information transfer control system
EP0064818A1 (en) * 1981-04-20 1982-11-17 Pitney Bowes, Inc. Data collision avoidance method
US4423482A (en) * 1981-06-01 1983-12-27 Sperry Corporation FIFO Register with independent clocking means

Also Published As

Publication number Publication date
JPH05505478A (en) 1993-08-12
IL95448A0 (en) 1991-06-30
KR920704225A (en) 1992-12-19
EP0512993A4 (en) 1993-02-24
WO1991011768A1 (en) 1991-08-08
EP0512993A1 (en) 1992-11-19
AU6431990A (en) 1991-08-21
CA2074530A1 (en) 1991-08-03

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