JPH05505478A - Bus-locking FIFO multiprocessor communication system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Bus-locking FIFO multiprocessor communication system 1, multiple FIFO City-Operating System Architecture-(MtJLTIPL εFACILITY RATING SY revised EM ARCHITEC direct staff), Inventor: David Hitz, Alan Schwartz (A llan Schmrtz), James Lau and Ga. Guy Iarris; Z parallel input/output network File server architecture - (PARALLEL [10NETWOR K FILE 5ERVERARCH [TECTIJRE], Inventor: Shonro John Row, Larry Boucher , William Pitts and Steep Bligh Steve Brightman; 3. Synchronous handshake and Sophistication using block mode data transfer■IE bus protocol t-:I-rule (EN HANCED VMEBUS PROTOCOL Lrr[LIZ[NGSYN CHRONOUS HANDrHAKI NG AND BLOCK MODE DATA TRANSFER), inventor : Daryl D Star (Daryl D, 5 tart); 4. High speed, flexible source and destination data burst Direct mail%’) 7’)’t: 7 Controller (HIGH5PE ED, FLEXIBLE 5O1JRCE/DESTIm AT[ON DATA BUR3T DIRECT MEMORY ACCES S C0NTR0LLER), Inventor: Dary lD, 5 tarr) The above applications are all assigned to the present invention, and FIELD OF THE INVENTION The present invention, attached hereto by reference, relates generally to the field of microcomputers; Buslocking FI especially for use in multiprocessor computer systems Regarding F○ communication.

Background of the invention In recent years, computer industry applications and office computing The evolution of computer system architecture is remarkable. “Smart” workstation is a “stupid” terminal connected to a mainframe or microcomputer. are gradually being expelled. These “smart” workstations are A computer with local processing capabilities and local storage. like this A “smart” workstation is equipped with a variety of processors, data storage devices, and communications devices. device, and a portion of a larger network that includes other peripheral devices.

A workstation network generally consists of individual user workstations. (referred to as “client”) and filing, data storage, printing and and shared resources for wide area communications (individually referred to as “servers”).

The client and server are connected to a local area network such as Ethernet. (“LAN”). Multiple Ethernet interconnected by the net.

Through Ethernet, the client provides data and storage facilities to the client. Typically connected to a server that provides the Mainly provides file storage access A server that does this is called a "file server." Traditional servers are It includes a central processing unit 1ii (“CPU”) coupled to the Ethernet. The CPU itself , connected to main storage. Both the CPU and main memory are connected to the same bus. It is connected to a conventional input/output device (“Ilo”). Using the bus, the CPU , communicate with a disk controller for mass storage purposes, or otherwise communicate with other peripheral devices.

Processor technology and performance have improved dramatically in recent years, but input/output performance has So far, it has not grown commensurately. Although the processing performance of the CPU is large, The overall performance of the system depends on the low performance threshold of Ilo achieved on the bus. Not surprisingly.

The performance level of any bus is limited by the amount of data transfer transactions that occur across the bus. It is determined primarily by the time it takes to execute. A tiger passes the bus. The transaction time required for each transaction is now as short as possible. When optimized, a bus can handle more transactions in a given amount of time. Becomes Noh. Therefore, in a given period of time, the bus handles a larger number of transactions. Performance will improve as it becomes possible.

The VME backbrain bus (hereinafter referred to as “VME bus”) is a This is one of the I10 buses in use. The VMEbus has been widely implemented and It has become the standard throughout the world. For this reason, the standards committee of the Institute of Electrical and Electronics Engineers (IEEE) The association established the VME bus standard and published the VME bus standard manual D1.2 version (VME bus Specification Manual Dl, 2nd edition) (hereinafter referred to as “VM E-Bus Standard), which is attached here as a reference. It will be done.

The standard VMEbus interface system is a backbrain interface Logic circuits, four groups of signal lines called “buses”, and signal lines a collection of functional modules that communicate with each other through a network. The four buses are for data transfer. transmission bus (“DTB”), arbitration bus, priority interrupt bus, and It is a tea bath. This application primarily relates to DTB.

The DTB connects the CPU and other intelligent controllers to the vME bus. A “master” is a functional module that starts the DTB cycle, such as a controller. allows the master to perform binary data transfers between itself and the “slave” shall be.

“The slave is the main memory that detects the DTB cycle initiated by the “master”. A functional module, such as a device, when these cycles specify its participation. transfers data to its “master” and also receives data from this “master”. Receive.

There are next seven DTB cycles to be executed on the “master” or DTB. write, block read, block write, read modification write, address only and interrupt response cycles.

In one read cycle, 1.2.3 or 4 bytes of parallel data is transferred from the master to the slave through the DTB. The master is the address After broadcasting the call and address modifier and placing the data in the DTB, the read cycle Start. Each slave collects addresses and address modifiers, and Decide whether to respond to the call. A slave that intends to respond will internally record the data. retrieves the data from the storage device, places it in the DTB, and acknowledges the data transfer. .

In one write cycle, 1, 2.3 or 4 bytes of parallel data or DTB and is transferred from the master to the slave. The master is the address After broadcasting the call and address modifier and placing the data in the DTB, the read cycle Start. Each slave collects addresses and address modifiers, and Decide whether to respond to the call. The slave(s) with the intent to respond will data and acknowledge the data transfer.

The block read cycle reads a block consisting of 256 bytes from l to the slave. This is the DTB cycle used for transfer from disk to master. blockley The transfer of a 2- or 4-byte wide column (i.e., data word width). Once the block transfer starts Then, the master does not release the DTB until all bytes have been transferred. Bro A read cycle is a read cycle in which the master sends only one address and address modifier. It differs from a read cycle column in that it broadcasts at the beginning of the cycle. . The slave gifts addresses for each transfer, and the data for the next transfer is The data is retrieved from the storage location.

The block write cycle is similar to the block read cycle, starting from ■ to 256 cycles. D used to transfer a block consisting of bits from the master to the slave. This is the TB cycle. Block write transfers can be performed using 1, 2 or 4 byte wide data transfers. This is done using data transfer. Once a block transfer begins, the master Do not release DTB until all bytes have been transferred. block light cycle The master sends only one address and address modifier at the beginning of the cycle. It differs from the light cycle queue in that it broadcasts. The slave is Each transfer presents an address and the data for the next transfer is retrieved from the next higher storage location. It's about to be served.

Read modification cycles allow other masters to access the slave's storage locations. write to and read from that slave location without This is the DTB cycle used for loading data.

An address-only cycle includes only one address broadcast cycle. day data is not transferred. The slave never responds to address-only cycles. Otherwise, the master ends this cycle without waiting for a response.

This means that in a fully "synchronous" system, the slave's response is irrelevant. This technique differs from “synchronized” systems in that the start of the DTB cycle is In the field, it is called “handshaking.” The master controls the data transfer cycle. After starting, the designated slave responds before the master finishes its cycle. wait for. Due to the asynchronous nature of the VMEbus, the slave requires You are allowed to spend as much time as possible. The VME bus uses one handshake sequence. It requires four propagations through the DTB to complete the process. slave However, the slave may malfunction and not respond, or the master may accidentally address itself to a location where the slave is not present. If the address is specified, the bus timer intervenes and ends the cycle.

The VMEbus standard monitors data that resides on functional modules and passes through the DTB. It specifies the use of position monitors to Each monitor is Operates to detect access to assigned location. These assignments A location monitor typically interrupts each time an access to one of its locations occurs. to that processor by a request signal. With such a configuration, the process processor B is located in the global V monitored by processor B's position monitor. When writing to ME bus storage, processor B is suspended.

DTB includes three lines: address line, data line and control line. nothing.

The master is numbered from number 2, referred to as address lines AO2 to A31. Line number 3I is used to select a group of four bytes for access.

Four additional lines, Day 9 strobe (DS(1), Data strobe 1 ( DS l *), address line 1 (AO+) and long word (LWOR D*) is the byte position within the four-byte group or is accessed during data transfer. used to select the The asterisk following the line abbreviation indicates that these The line is in the “low operating state” (i.e., when driven low, it is in the operating state). ). Using these four lines, the master can Depending on the type of memory, 1, 2, 3 or 4 byte locations can be accessed simultaneously. .

The DTB has six address modifier lines that allow the master to: Additional binary information can be streamed to the slave during data transfer. 64 types of changelings These are available in three categories: defined, reserved, and user-defined. It can be divided into either layer. User-defined codes can be used to create any It can also be used for any purpose. Typical usage of user-defined code is page change, memory protection, master or task identification, privileged access to resources, etc. D Actual data transfer is performed on the 32 data lines from OO to DS1 or on the bus. .

The master can access up to four byte locations at the same time. Master is a Once you have selected the byte locations you want to access, you can Binary data can be transferred between devices.

DTB is address strobe (AS*), data 9 strobe 0 (DS(1 ), data strobe I (DS1*), bus error (BERR*), data transfer Six controls for transmission acknowledgment (DTACK*) and read/write (WRITER) Including your line. According to the VMEbus standard, the control line must be driven low. It states that the system must be thought of as ``operating.''

AS) The falling edge of the k line signals the broadcasted alarm to all slave modules. Notice that the dress is stable and collectable.

DS(l and DSl* add their function in byte position selection for data transfer. In addition, it also has a control function. In a write cycle, the first rising of the data strobe A falling edge indicates that the master has placed valid data on the data bus. and In a read cycle, the first rising edge is more valid than the DTB. Notifying the slave that data can be removed.

The slave can perform a write cycle by driving DTACK* low. indicates that the data was successfully received.

In a read cycle, the slave retrieves data by driving DTACK* low. indicates that it has been placed in the DTB.

The BERR* line is an open signal driven low by a slave or bus timer. This is a signal from the open collector that indicates to the master that the data transfer was unsuccessful. vinegar. For example, if a master tries to write to a location that has read-only memory The responding slave will then drive BERR* low. Is the master squid? Accessing a location that is not even given by a slave causes the bus timer to However, after a specified period of time, BERR* goes low.

WRITER is strobed by the leading edge of the first data strobe. This is the level valid line to be blocked. This indicates the direction of data transfer by the master. used for When WRITER is driven low, the data transfer direction is , from master to slave. When WRITER is driven high, the data The transfer direction is from slave to master.

The VMEbus standard requires four separate propagations across the VMEbus. It stipulates doshake. The master asserts DSO* and DSI*. , begins a data transfer cycle. Assertion of master's DS (l and D31*) In response to this, the slave asserts DTACK*. DT8 by master In response to the assertion of K* to to In response, the slave deasserts DTACK* to complete the wake. These four propagations are necessary to complete the handshake. It is.

The maximum transfer rate across a typical VME bus is 20 to 30 megabytes per second. range. However, from one device on the VMEbus to another device on the VMEbus When large amounts of data must be transferred quickly or when many data transfers are required. If necessary, this level of transfer rate is slow enough to introduce processing delays.

VME backplate bus for maximum data transfer speed and processing efficiency The transfer rate of data passing through must be increased.

Another important feature of the VMEbus architecture is that “message It is a “message” passing system realized to pass “. The message “passing system” is a disk drive controlled by a disk controller. from the CPU controller to read a specific block of data on the disk. Contains messages to the disk controller. Various treatments or various It's working on functional modules, so from one module to another It becomes necessary to send a "message" via the bus.

The most common method of forwarding messages is generally the “postal port” for message forwarding. This is called the strike method. Under the Postal Post Act, messages to be forwarded can be sent The processor to which the message is sent is called the “sender.” Sir is called "recipe end". configured to be suitable for receiving messages. All new processors are equipped with a "postbox."

Processors located in various functional modules store “messages” Allocate memory for a purpose. Messages typically grow a fixed length of 128 bytes. vinegar. Therefore, various processors store 128 bytes in the "message buffer". Allocate memory. To start sending a message, the sender uses the specified Inserts the message sent to the recipe end into the message buffer. Metsuse The recipe must then be transferred to the recipe end.

The sender is a traditional VME bus line address addressed to the mailbox at the recipe end. Start operation. If the data read from the postbox at the recipe end If the data is “zero”, this indicates the available space for the postbox at the end of the recipe. It shows that there is a lot. The sender then uses a write operation to the end of a recipe by sending a “pointer” on the VME bus using You can freely write the pointer on the mailbox. “Pointer” is the sender's menu. Contains the address of the message forwarder.

If the data read from the mailbox is non-zero, the mailbox at the end of the recipe The post is a post, and the sender is a pointer to the mailbox at the end of the recipe. You need to wait a preset amount of time before checking if you can write the file. in advance After a set amount of time, the sender will be available to the postbox at the end of the recipe. A lead operator who addressed the mailbox to see if there was an available slot. start the session. When the sender detects an available slot, it immediately fills the mailbox. Invoke a write operation to place the pointer in the list.

The recipe end monitors its mailbox for incoming pointers. . As soon as the pointer is received, the recipe ends with the sender's message buff. Invoke a sequence of read operations to retrieve the message from the server. do.

The processor at the recipe end processes one postal port for each potential sender. must have a strike. This one-to-one condition means that one postbox If you do not dedicate one sender, two different senders can use the same mailbox at the same time. The need to be met is due to the fact that collisions occur when writing to . With conventional technology The recipe ends with one postbox for each potential sender. This avoids such conflicts. Recipe end processors typically handle multiple postal each of which corresponds to one particular potential sender.

At the recipe end, each potential sender must have one postbox. This uses a large amount of recipe end memory to set up all postboxes. Ru. Furthermore, each recipe end can simultaneously receive messages from many different senders. By providing a large number of postboxes with receiving functions, these large numbers of postboxes can be The time it takes to poll all of the mailboxes is the same as polling just one postbox. This will take significantly longer than it would take to do so.

If high-speed transfer is the goal, the postal mail method is the least desirable method. Post The post method requires multiple transactions on the VME bus. mentioned above As in, the sender first detects the availability of slots in the postbox. , the read operation must be invoked at least once, if not multiple times. Must be. To place the pointer in the mailbox at the end of the recipe, the sender must initiate a write operation. The end of the recipe is Metsu To retrieve the sage, a read operation must be invoked next. . These numerous transactions on the VME bus consume bus time and Therefore, overall performance is degraded.

As described above, we have developed a high-performance message transfer system that is compatible with the VMEbus standard. There is a need to

So far, increasing transfer speeds beyond the 20-30 MB per second range On that front, there has been little progress. Adhering to the VMEbus standard limits data transfer on the VMEbus. There are problems in terms of improving transmission.

The good acceptance of the VMEbus is primarily due to the widespread adoption of the VMEbus standard. Due to its compatibility with systems and peripherals, it has a wide range of applications and industries.

As a result of maximizing this compatibility, there will be no delay in efforts to improve VME bus performance. was brought. Compatible VMEbus architecture - VMEbus Must be consistent with standards. The performance issue is that if compatibility is maintained, the VM This must be resolved within the premise of the E-bus standard.

Summary of the invention The present invention provides a method for transmitting data from a first processor (the "sender") to a second processor on the bus. Message transfer system for transferring message data to (“recipe end”) Regarding the stem. The message forwarding system transmits messages forwarded from the first processor. Contains a FIFO connected to the bus for receiving and storing message data. It has a station where FIFO stores message data. has a FIFO full status indicating that it is not possible to Occurs to indicate that a FIFO full condition exists. The system further includes FI If a write cycle is initiated while the FO or FIFO full signal is being generated, The sender processor uses a bus error signal instead of the normal DT8 signal. FIFO means for responding on the VME bus to FIFO write cycles from and means connected to the VME bus.

The present invention allows messages to be sent from one processor to another through a To provide a device and method for efficiently and quickly transferring data. According to the present invention Efficiency and high speed are primarily due to the minimization of transactions on the bus. . The number of bus cycles required to perform a message data transfer on the bus is Has been reduced to a single write cycle. This is the message date mentioned above. In contrast to traditional message transfer systems that require many cycles to transfer data, This is a significant improvement.

Additionally, the present invention allows each process to process message data from all senders. Only one FIFO is required per server. Similarly, this Requires the sender to have one postbox for each potential sender. This is a significant development from the previous system, which required a lot of effort. recipe end processor The use of one FIFO per FIFO reduces the hardware required to perform message data transfers. This has the effect of significantly reducing hardware and simplifying the polling function. be. The recipe end processor uses one FIF for message data. As you can see, many postboxes are polled for message pointers. There is no need to log.

It is an object of the present invention to reduce the hardware requirements required to perform the message transfer function. multiprocessor to greatly simplify management of message transfers. The purpose is to provide a communication system.

Brief description of the drawing FIG. 1 is a block diagram illustrating a preferred embodiment of the support hardware of the present invention.

Figure 2 shows how the data transfer bus is connected to the master device as required by the VMEbus standard. FIG. 2 is a block diagram illustrating main signal lines logically connected to functional units.

Figure 3 shows how the data transfer bus is connected to the slave device as required by the VMEbus standard. FIG. 2 is a block diagram illustrating main signal lines logically connected to functional units.

Figure 4A is a timing diagram illustrating the conventional VMEbus standard handshake protocol. It is a chart.

FIG. 4B is a time chart illustrating the high-speed transfer mode handshake.

FIG. 5A shows a standard VME for referencing data during a block write cycle. It is a time chart explaining a bus protocol.

FIG. 5B shows the present invention for referencing data during a block write cycle. 3 is a time chart illustrating a high-speed transfer protocol according to the present invention.

FIG. 6 Δ is the mark #! for referencing data during the block read cycle. V.M. It is a time chart explaining E/< protocol.

FIG. 6B shows the present invention for referring to the period number data of the block read cycle. 3 is a time chart illustrating a high-speed transfer protocol according to the present invention.

Figure 7A illustrates the operation of the fast transfer protocol during a block write cycle. This is a flowchart.

FIG. 7B is a continuation of the flowchart of FIG. 7A.

FIG. 7C is a continuation of the flowchart of FIG. 7B.

Figure 8A illustrates the operation of the fast transfer protocol during a block read cycle. This is a flowchart.

FIG. 8B is a continuation of the flowchart from FIG.

FIG. 80 is a continuation of the flowchart of FIG. 8B.

Figure 9 shows data transfer related to high-speed transfer mode of block write operation. It is a time chart showing timing.

FIG. 9A illustrates a data transfer cycle inserted into the box 900 location in FIG. It's clear.

Figure 10 shows the data transfer associated with the high-speed transfer mode of block read operations. It is a time chart showing transmission timing.

FIG. 10A shows a data transfer cycle inserted into the box 1000 position in FIG. 1O. It explains the rules.

FIG. 11 shows a modified thread of a data transfer bus implemented in a preferred embodiment of the present invention. A block diagram illustrating the main signal lines that logically connect to the server functional units. be.

FIG. 12 is a flowchart explaining the message data transfer operation performed in the present invention. It is the default.

FIG. 13 shows a bus-locking FIFO multiprocessor communication system according to the present invention. FIG.

FIG. 14 shows a bus-locking FIFO multiprocessor communication system according to the present invention. 1 is a block diagram of one preferred embodiment of a processor used in the system; FIG.

FIG. 1 shows a preferred embodiment of the support hardware of the present invention, indicated generally by the reference numeral 10. FIG. 2 is a block diagram of an embodiment. 10 Preferred Hardware System Architects The char is based on the related application parallel input/output network file server architecture mentioned above. tech-)-t-(PARALLEL Ilo NETWORK FILE 5 ERVERARCHITECTURε) and is available here as a reference. Attach to.

The hardware components of the system IO are comprised of multiple network components in this example. controller 12, file system controller 14, broadband backbrain It includes large storage capacity processors 16 interconnected by bus 22 . These controllers Each of the controllers 12.14 and 16 is equipped with a high performance processor and a local controller. It is preferable to have a program storage device of the same type, so that access to bus 22 minimizes the need for Bus 2 with controllers 12.14 and 16 2, controller 12.14.16, system Control information and clocks are transferred between memory 18 and local host processor 20. Transfer access required to transfer client workstation data It is preferable to substantially limit the

The configuration of the illustrated system 10 includes four network controllers 12A to 1 2c, two file controllers 14A and 14B, two large storage capacity processors 16A and 16B, four system memory cards 18A to 18 A local host connected to the breadboard and backbrain bus 22 consisting of includes a processor 20. Each network controller (NC) 12 has a Pair of networks controlled by the 68020 processor of the controller, 3 ．． It has connections with two independent Ethernet networks, denoted 5 and 7. That's preferable. Each network connection is a traditional Ethernet network connection. Directly supports data transfer of 10 megabytes per second, which was subsequently specified. of the present invention The preferred embodiment therefore has a potential total maximum data throughput of 80 megabytes per second. have power.

The file controller (FC) 14 is mainly a special computer engine. each of which is designed to operate on a high-performance Motorola 68020 machine. System using icropro sensor and 2 medabytes of local program memo and a smaller half-megabyte high-speed data storage device.

Large storage capacity processor (SP) 16 is an intelligent small computer - Operates as a system interface (SCS I) controller. So Each is equipped with a high-performance Motorola 68020 microprocessor-based system and , 2 megabytes of local program and data memory, and lO parallel an array of five CSI channels. Drive arrays 24A and 24B are , connected to a storage processor to provide large storage capacity. drive Arrays 24A, 24B have a width of 10 units of SCS I storage and are uniformly It is preferable to grow from 1 to 3 units deep. Preferred embodiments of the invention In this case, each unit of arrays 24A and 24B has a conventional 768 MB 51/ A 4-inch hard disk drive was used. Therefore, at each drive array level grows approximately 6 GB of storage capacity, and each storage processor easily supports 18 GB. The system has a total data storage capacity of 36 GB. .

In a preferred embodiment of the invention, local host processor 20 is a Sun Mi Model 5un3E manufactured and sold by crosystems, Inc. , a Sun 3/40 central processor card.

Finally, each of the system memory cards 18 is stored within the computer system 10. Provides 32 megabytes of 32-bit memory for shared use. This message The memory is under the control of each of the system 10 processors.

In a preferred embodiment of the invention, VME bus 22 is connected to network controller 1 2. File controller 14, storage controller 16, system memory 18 and local host 20 for interconnection. VME bus 22 The hardware control logic for controlling the As implemented on controller 12 and storage processor 16, It has been enhanced to support Ming's Busmaster high-speed transfer protocol.

System memory 18 also includes modified slave VME bus control logic according to the present invention. A network controller 12 and a storage processor 16 System memory as data transfer data source or data transfer destination for -18 is now working.

The configuration of System 10 represents an initial preferred maximum hardware configuration; , the invention provides a suitable type or number of controllers or disk drives. is not limited to the preferred size and type of tube.

■ Overview of high-performance VME bus Figures 2 and 3 illustrate representative master and slave functional units ( Hereinafter, it is a block diagram of a "master" and a "slave".Data transfer bus The signal lines connecting master and slave through (DTB) are shown in Figure 2 and Figure 2. 3, and there are: AOI-Al1' Address Bus (bits 1-15) - Short, IIJ! '! quasi , or a three-state driven address line used to broadcast extended addresses.

A16-A23 Address bus (bits 16-23) - standard or extended address A three-state drive address line used in conjunction with AO1-A15 to broadcast hmm.

A24-A51 Address bus (bits 24-31) - Broadcast extended address A tri-state drive address line used in conjunction with AOI-A23 for.

AMO-AM5 address modifier (bits 0-5) - address size, cycle Used to broadcast information such as type and/or master identification 3-state drive line.

AS address strobe - A valid address is placed on the address bus A three-state drive signal indicating the hour.

BERR* Bus error - an error caused by a slave or bus timer. Bun collector drive signal, this signal indicates that the data transfer is not completed. Show to master.

DOO-DS1 data bus - Used for data transfer between master and slave 3-state drive bidirectional data line.

DSO*, DSl* Data strobe O and l - how many data nodes ( LWORD and AOI to indicate whether l, 2.3 or 4) is being transferred. 3-state suspension drive signal used in connection with. During the write cycle, the first data The falling edge of the bus indicates that valid data is available on the data bus. shows. In a read cycle, the rising edge of the first data strobe indicates that data has been received by the data bus.

DTACK* Data Transfer Acknowledgment - 3-state drive generated by slave It's a signal. The falling edge of this signal is placed on the data bus during a read cycle. indicates that valid data is available, or during a write cycle. indicates that data has been received from the data bus. The rising edge is the lead side. Indicates when the slave releases the data bus at the end of the cycle.

LWORD* Long word - Any one of the 4-byte groups during data transfer 030 line, DSl* and AOI to select the byte position(s). Three-state drive signals used in conjunction.

WRITE* Write - Data transfer cycle is read cycle or write cycle A three-state drive signal generated by the master to indicate whether the signal is active or not. high level is , indicates a read operation, and a lower level indicates a write operation.

As shown in FIG. 2, the slave function module 200 includes a backbrain input. The interface logic circuit 210 is logically connected to the interface logic circuit 210. back brain interface The interface logic circuit 210 is connected to the data transfer bus lO by a signal line 220. It is connected. The traveling direction of the signal on the signal line 320 is the direction of each arrow. Indicated by The DTACK* signal line originates from the slave and connects to the conventional It is continued. The direction of travel of the signal on the signal line 320 is in the direction of each arrow. Therefore, it is shown. The DTACK* signal line is generated in the slave and is the conventional 64m A. Driven by a three-state driver. The data lines are shown in Figure 2. Of course, it goes both ways.

As shown in FIG. 3, the master function module 300 includes a backbrain input The interface logic circuit 310 is logically connected to the interface logic circuit 310. back brain interface The interface logic circuit 310 is connected to the data transfer bus IO by a signal line 320. It is connected. The traveling direction of the signal on the signal line 320 is the direction of each arrow. Indicated by DS (1, DSI, AS* and AMO to AM5 signals The line is originating from the master. Data lines DOO to DS1 are shown in Figure 3. As shown, it is of course bidirectional.

■High-performance VME bus high-speed transfer protocol The present invention provides handshaking and devices on the VME bus by reducing the number of bus propagations required to implement Data transfer speed is increasing.

Figure 4 shows the conventional hand-engineering protocol defined by the VMEbus standard. It shows. Hazards using traditional VMEbus handshaking protocol Four bus propagations are required to perform the handshake. The master is Asserting DS(1, DSl*, shown as propagation l in Figure 4A, on the DTB) Start data transfer by Next, the designated slave transmits propagation 2 in Figure 4A. Assert DTACK* indicated by . master driven by slave As soon as the asserted DTACK* is received, the Deasserts DS(l and SDI tree. Slave deasserts DSO* and As soon as it receives the deassertion of DSl* and DSl*, the , DTAKC* is deasserted. Deassertion of DTACK by slave and the handshake is complete.

FIG. 4B is a time chart showing the fast transfer mode handshake protocol. be. There are only two bus propagations used to perform the handshake.

At the beginning of a data transfer cycle, the master asserts DSO* and transmits the signal in Figure 4B. Deassert DSO* in the form of a pulse of width in the manner shown in Figure 1.

Deassertion of DSO* occurs regardless of whether a response is received from the slave or not. , executed. Therefore, the DSO* signal is completely separate from the DTACK* signal. has been done.

The master must then cross the acknowledgment from the slave. Subsequent DS The O* pulse is generated until a response DTACK* signal is received from the slave. , is impossible. As soon as the slave's DTACK* assertion is received, the As shown in Propagation 2 of B, the master will immediately send the device if so requested. Assert data strobe. The fast transfer mode protocol according to the present invention includes: DTAC is asserted by the slave as a precondition for subsequent assertion of DSO*. There is no need for the master to wait until K* is deasserted. Fast transfer mode In this case, only the leading edge (ie, assertion) of the signal is important. this As such, deassertion of DSO* or DTACK* completes the handshake. It becomes completely irrelevant to

The high-speed transfer protocol of the present invention uses the DS1* line for data strobe purposes. stomach. DSO* and DSl* are driven by different drivers, so The queuing problem occurs very well.The skew between DS(l and DSl* is the delay in asserting the data strobe condition required to signal a data transfer. cause. Therefore, in the present invention, the DSl* line is used for handshake processing. Not used. In the high-speed transfer mode protocol of the present invention, the data strobe For our purposes, the skew problem can be removed by referring to the DSO* .

The Fast Transfer Mode protocol contains both synchronous and asynchronous features, so Characterized as quasi-synchronous. The fast transfer mode protocol allows the DSO* to due to the fact that it is asserted and deasserted regardless of the response from the slave. If so, it has the characteristic of synchronization. The asynchronous feature of the Fast Transfer Mode protocol is that 0 until the master receives a response to the previous strobe from the slave. This is attributed to the fact that 80 lines are not asserted next. Therefore, the present invention Since it includes asynchronous and asynchronous elements, it is most accurately classified as "pseudo-synchronous."

Figure 5A shows the standard VME bus protocol for data references during block write cycles. FIG. Standard VME bus block write operation In this case, the data to be transferred is broadcasted and sent to the master, as shown in Figure 5A. asserts DSO3 and DSI. The slave receives the data and Assert DTACK*. In standard VME protocols, valid data are: The thread continues for a known time interval after DTACK* is asserted by the slave. Guaranteed to be broadcast live. The master continues to check whether valid data is being broadcast, but deasserts DS(llk and D31*. The write cycle is completed as soon as DTACK* is deasserted by the slave. .

FIG. 5B shows a high-speed data reference according to the present invention for data reference during a block write cycle. 3 is a time chart illustrating a fast transfer protocol. block light cycle The transfer of data within is only referenced for DSO*, as shown in Figure 5B. Ru. The master broadcasts valid data to the slaves. The master then Assert DSO to the slave as shown in . Slave is DS After the assertion of O*, data collection is done during that time, as shown in Figure 5B. A preset time interval Tc is given. DTACK* during transfer cycle is not referenced, so the slave module is ready to collect data at any time. I have to do it.

FIG. 6A shows the standard #VME server for referencing data during the block read cycle period. It is a time chart explaining a protocol. Standard VMEbus Blockley In the de-operation, the master has the DSO* and Assert DS1*. In response to the assertion of DSO* and DS1*, the thread The bus broadcasts the data to be transferred over the bus and asserts DTACK3k. Ru. Valid data remains on the master for a period of time after assertion of DTACK* by the slave. It is guaranteed that broadcasting will continue on the same day. Master is valid data or broadcast Deassert DSO* and DSI* even if ongoing. block lead The cycle ends with the deassertion of DTACK* by the slave.

FIG. 6B shows a method according to the present invention for referencing data during a block read cycle. 3 is a time chart illustrating a high-speed transfer protocol. block lead cycle The transfer of data during the period is referenced only to DTACK*, as shown in Figure 6B. It will be done. The master asserts DSO*. The slave is shown in Figure 6B. uni, broadcast data to the master and assert DTACK*. fast transfer pro In a call, the master is shown Figure 6B after asserting DTACK*. Given a preset time interval Tc during which data is collected, It will be done. The DSO is not referenced during the transfer cycle, so the slave module However, you must be prepared to collect data.

Figures 7A to 7C illustrate the high speed transfer protocol block write cycle of the present invention. It is a flowchart showing operations required for execution. Block write cycle open To begin, the master identifies the memory address and address of the data to be transferred. broadcast the program modifier over the DTB bus. The master also receives an interrupt response signal. (IACK*) high and LWORD* signal o+:Il[mt6.7 The 010IACK* signal is used to respond to interrupt requests from the priority interrupt bus. Standard VMEbus protocol signals used.

A special address modifier broadcast by the master sends high Indicates that fast transfer protocol is used to perform block writes.

In one embodiment of the present invention, the VMEbus standard provides one user-defined address modifier. The hexadecimal address modifier “If” is broadcast to the slave and the fast transfer program Indicates that a rotor call is used. Any user-defined address changes Note that Sarako can also be specified as a Fast Transfer Protocol address modifier. It should be seen.

The starting memory address of the data to be transferred must be on a 64-bit boundary. , the size of the block of data to be transferred must be a multiple of 64 bits. stomach. To maintain consistency with the VMEbus standard, the block must be updated to a new address. Do not cross a 256-byte boundary without performing a cycle.

Slave modules connected to the DTB receive broadcasts from the master via the bus. low LWORD* and high I 703° broadcast address and address modifier receiving ACK*, 701 , immediately after, the master drives the 705° slave module low, driving the AS* signal low. The slave receives the raw AS* signal, 707°.Each slave individually receives the broadcast participate in this data transfer by determining whether the specified address is valid for each slave. If the 709° address is not valid, the data transfer The transfer is not related to that particular slave, and that slave is responsible for the rest of the data. Ignore data transfer cycles.

The master acknowledges the transfer that is about to occur by driving WRITE* low. The 711° slave indicates a cycle or a write cycle, and the low WRI TE main signal is received, 713, this data transfer operation is a write operation. The change from high to low on the DS (l signal line) The 715° master waits for the reception of the DTB when the previous slave is no longer driving the DTB. Wait until DTACK* and BERR* are high, indicating that Yes, 718° The master transfers the first segment of data to be transferred from data line DOO to After placing data from 719°DOO to DS1, the master , DS(l driven low, 721, after a preset time interval, DS0)k Drives to high, 723° 721.723 and SLE, respectively, in response to a high-to-low change in DSO*. The block transfers the data sent by the master from data line DOO to DS1. The 725° latch operation, which applies the latch, is based on the DSO* signal. It must be noted that only when the High-speed transfer program according to the present invention In rotocalls, DTACK* is placed on the data line by the master. It is not referenced for the purpose of latching the stored data. The master controls the data being transferred. Place the next segment from data line DOO to DS1 and Waiting until reception is received in the form of a change from high to low, FIG. 7B, 729° view As shown in 7B, the slave drives DTACK* low, 731, and by a 733° slave that drives DTACK* high after a set period of time. latched, 725, data is selected for storage. The 735° slave also presents the device address. 735° slave also waits for further change of DS(l from high to low). machine, 737° To begin transferring the next segment of the block of data to be transferred, the master - drives DSO* low and 739, after a preset time interval, DSO 741° DS (responsive to a high-to-low change in l) that drives the tree high. Nozore 739.741, the slave receives the data signal being broadcast by the master. The 743° master, which latches the data on DS1 from InDOO, transfers Place the next segment of data from data line DOO to DS1, 74 5. Wait until the DTACK* signal is received in the form of a change from high to low; 747° The slave then drives DTACK* low, 749, for a preset time. After the interval, the latch is latched by the 7510 slave, which drives DTACK* high. 743, the data is written to the device selected to store the data. 735, the device address is assigned, 753° the slave also has a DS 737° data transfer waits for further change of O* from high to low. , continue as described above until all of the data has been transferred from the master to the slave. . After all of the data has been transferred, the master connects the address line, address modifier line, data line, IACK* line, LWORD* line and DS(l To release the line, the 755° master changes DTACK* from /1 A to LOW. The 757° slave drives DTACK* low and waits to receive the 757° signal. 59. Drive DTACK* high after a preset time interval, 761° In response to receiving a high-to-low change in DTACK*, the master sets AS* to Drive high, 763, release AS* line, 765° Figures 8A to 80 , the operations required to execute the high-speed transfer protocol block read cycle of the present invention. FIG. To start a block read cycle, The controller sets the memory address and address modifier of the data to be transferred to the DTB buffer. broadcast through 801. The master drives the LWORD)k signal low. , drives the interrupt response signal (IACK*) high, 8010 as already mentioned. In addition, special address modifiers are used to configure fast transfer protocols for slave modules. indicates that the file is used to perform a block read.

Slave modules connected to the DTB receive broadcasts from the master via the bus. The address and address modifier specified are received, and rows LWORD* and /% input are received. When broadcasting an 803° address and address modifier that receives an IACK*, 801, immediately the master drives the AS* signal low, 805° slave The module receives the raw AS* signal, 807°. Each slave individually receives the This data transfer is performed by determining whether the sent address is valid for each slave. If the 809° address is not valid, the data The data transfer is not related to that particular slave, and that slave Ignore data transfer cycles.

The master acknowledges the transfer that is about to occur by driving WRITE* high. The 811° slave indicates a cycle or a read cycle, and the 11i WR ITE* signal is received, 813, this data transfer operation is a read operation. the first segment of the data to be transferred. The 819° master placed from Tarain DOO to DS1 is DTACK* and BERR* or NO\, indicating that the DTB is no longer being driven. Wait until the state is 818° The master drives DSO* low, 821, after a preset time interval. The 823° master that drives DSO* high is the DTACK* signal line, The slave waits for a low to high transition at 824°, as shown in Figure 8B. 825, after a preset time interval, the DT 827° DTACK* high-to-low change that drives the ACK* signal high 825.827, respectively, the master connects data lines DOO to D 8310 latch that lunches data sent by slave to S1 Note that the operation only responds to the DTACK* signal. Must be. In the fast transfer protocol according to the present invention, the DSO* unreferenced for the purpose of launching data placed on the data line by stomach. 831, data latched by the master, stores the data. 833° is written to the selected device to send the device address. The slave transfers the next segment of data to be transferred from data line DOO to DS. 1, 829, wait for further change of DS(l from high to low, 837 ゜To start the transfer of the next segment of the block of data to be transferred, The controller drives DSO* low and, after a preset time interval, 829, the DS The 8410 master driving O* high is the DTACK* line or )\I? Waiting for it to change to low, 843° The slave then drives DTACK* low, 845, for a preset time. /% squid angle of 847° DTACK*, driving DTACK* high after interval In response to the change to row, 839 and 841, respectively, the master The data sent from data line DOO onto DS1 is The data latched by the 845° master is the 845, data 80.851, device address is given as a gift. The slave transfers the next segment of data to be transferred. The transfer of 849° data placed on DS1 from line DOO is from the slave. All data transferred to the master is transferred to the device selected to store the data. Continue as described above until it is written.

After all of the data to be transferred has been written to the storage device, the master In, address modifier line, data line, IACK* line, LWORD* The 852° master that releases the DTACK* line and the DSO* line 853° slave waiting to receive a high to low change DTACK* 855, after a preset time interval, drives DTACK* low. In response to receiving a high-to-low change in 857° DTACK*, driving Master drives AS* high, 859, releases AS* line, 861 0 Figure 9 shows the data transfer associated with a fast transfer mode block write operation. It is a time chart explaining timing.

As shown in FIG. 9, the address of the location where the data is to be transferred is the line AO It will be broadcast on A31 from 1. address modifier code, including the fast transfer mode address modifier code. The dress changer is broadcast on AMS from line AMO by the master.

Once the address and address modifier are set on their corresponding lines, The master drives AS* low. The WRITE* line is controlled by the master. As mentioned above, the next operation is to write Indicates that it is an operation.

DS1 line is not used during high-speed transfer mode operation. , may or may not be asserted throughout the operation.

After driving the WRITE* line low, the master writes the first Broadcast the segment from line DOO on DS1.

DSO* is driven low and this signal then goes to /% input as shown in Figure 9. is deasserted. Broadcast by master as DSO* The input data is driven low and the data is The latch is applied by rapping. After DSO* is driven low, the master , the next segment of data to be transferred is transferred to line DOO or Then broadcast to the slaves on D3+. In response to DSO* being driven low. In response, the slave drives DTACK* low for a period of time and then drives this signal low. data transfer by deasserting the DTACK signal high on the DTACK* line. Execute the response to. As shown in FIG. 9, DSO* indicates that the slave It will not reassert until it responds by driving the TACK* line low.

As mentioned above, a data transfer cycle consists of either all the data to be transferred or released to the slave. Continue until sent. The number of cycles required to complete the transfer is shown in the box in Figure 9. Occurs in Kus900. Box 900 is for illustrative purposes only and specifically It doesn't say if you want to use kale.

11N9A is the data transfer cycle inserted at the location of box 900 in FIG. It shows. As shown in FIG. 98, DSO* is driven low. Row D In response to the SO* signal, the slave receives the data that was broadcast when DSO* went low. latch the data. Master broadcasts the next segment of data to be transferred do. The slave sets DTACK* low in response to the data transfer. This o The operation continues until all data has been transferred.

Referring again to FIG. 9, after completing the data transfer operation, the slave Set TACK* to low. In response, the master pulls the As* line high. to deassert AS*. The master also writes this WRITE Drive In high to release the WRITE* line.

The spacing between the DSO* and DTACK* signals depends on the application and system used. It depends and changes. Between the assertion of DSO* and the assertion of DTACK* The spacing will also vary depending on the application and system used. DSO* signal and DTACK* signal intervals, and the assertion of DSO* and DTACK* It is obvious that the data transfer rate increases if the interval between assertions of Ru.

Figure 10 illustrates data transfers associated with a fast transfer mode block read operation. It is a time chart showing timing.

As shown in Figure IO, the address of the location where the data is to be transferred is The dress changer is broadcast on AMS from line AMO by the master.

Once the address and address modifier are set on their corresponding lines, The master drives AS* low. WRITE* line is master Indicates that it is an operation.

The DS1* line is not used during high-speed transfer mode operation, so , is maintained high throughout the entire operation.

In response to the WRITE* line being driven high, data is written by the slave. It will be broadcast on D31 from InDOO.

DSO* is driven low and this signal then goes high, as shown in Figure 10. is deasserted. In response to DSO* being driven low , the slave drives DTACK* low for a period of time and then drives this signal to D Deasserts by driving high on the TACK* line to indicate a data transfer. execute the response. The data broadcast by the slave as DTACK* is , driven low by the master in response to the DTACK* signal driven low. latches. After DTACK* is driven low, the slave transfers The next segment of data to be processed is transferred from line DOO to D as shown in FIG. 31, broadcast to the master. DSO* indicates that the slave receives DTACK* It will not reassert until it responds by driving the pin low.

As mentioned above, a data transfer cycle is a cycle in which all the data to be transferred is released to the master. Continue until sent. The number of cycles required to complete the transfer is shown in the box in Figure 10. Occurs at 1000x. Box 1ooo is for illustration only and in particular It is not drawn according to a time scale. FIG. 10A shows box 1 in FIG. It shows a data transfer cycle inserted at location 000. Shown in Figure 10A As shown, DSO* is driven low. In response to the low DSO* signal, the thread The server responds to data transfers by driving DTACK* low. Lowe's DTA In response to the CK* signal, the master broadcasts when DTACK* goes low. Latch the data. The slave broadcasts the next segment to transmit.

This operation continues until all data has been transferred.

Referring again to FIG. 10, after completing the data transfer operation, the slave: Set the DTACK book to low. In response, the master AS* is deasserted. The master similarly writes this WRITE* Release the line.

As already explained regarding the write operation lane, the DSO* signal and DTA The spacing of the CK* signals will vary depending on the application and system used.

The interval between assertion of DSO* and assertion of DTACK* also depends on the application and and the system used. DSO* signal and DTACK* signal interval and the interval between the assertion of DSO* and the assertion of DTACK*. Obviously, if it is made smaller, the data transfer rate increases.

High-speed transfer protocols require that the data signal be present on the DTB for a very short time. Therefore, the skew between control and data signals must be minimized.

For example, the DTACK* signal that refers to data transfer in block read cycles is , at the maximum time, so that the master or the transferred data can be collected under all circumstances. Must change from high to low in the shortest possible time to provide pause. .

Traditional 64mA, 3-state driver 24 to implement high-speed transfer protocols 5 is a conventional slave module to drive DTACK* as shown in Figure 1■. It is used in place of the 48mA open collector used in Joule. . An alternative to this is that the 48mA oven collector DTACK driver is the same as the present invention. If it is not possible to drive DTACK* from high to low quickly enough to meet the purpose of It is necessary for the following reasons. 64mA, 3-shaped suspended driver 245 can be used with DTAC Provides a means of quickly changing the state of the K* signal and is therefore well suited to the purpose of the present invention. This reduces the skew between the DTACK* signal and the data signal.

Similarly, the master module and slave module data drivers are also changed. It must be noted that changes have been made. High-speed transfer in a preferred embodiment of the present invention In order to realize the protocol, the traditional VMEbus data driver is Must be changed to a 64mA, 3-state driver in type package.

This change is based on the actual driver package's own ground lead inductor. thus reducing the skew between data, DSO* and DTACK*. Reduces the "ground lead" effect that is a contributing factor.

Additionally, the signal return input along the bus backplane is optimized for maximum performance. The conductance is the short signal generation required to perform a fast transfer mode protocol. Is it necessary to reduce it to a level that allows movement? In a preferred embodiment of the invention, the signal The return inductance is the signal return and combined bin inductor. Connector stem with more ground bins to minimize is used to reduce. An example of such a connector is Teradyn “High Density Plus” connector manufactured by eCorporation, The model floor is 420-8015-000.

■、Haslocking FIFO message bashing protocol high-speed transfer program While Rotocall provides convenient block transfer of message data, the present invention Additionally, similar conveniences for inter-processor message descriptors can also be used in combination. provides a transfer method. In the preferred embodiment of the invention, these message descriptors are , a processor that receives message descriptors for locating data blocks. transfers the necessary information to start the accelerated transfer protocol block transfer. used for

Figure 2 is a flowchart illustrating a message descriptor transfer operation performed in the present invention. -This is a chart. The sender processor (hereinafter referred to as “sender”) is lff1 Although not shown in Figure 12, a recipe end processor (hereinafter referred to as Although not shown in Figure 12, the FIFO 1 connected to , initiates a message descriptor transfer by invoking a write cycle for . The 1010° message descriptor contains any type of data. representatively The message descriptor contains data parameters of 128 bytes. of the present invention In a preferred embodiment, the message descriptor includes a message descriptor recipe end process. Contains the shared memory address of the data block to be transferred to the server. this recipe The end processor uses the shared memory address given by the message descriptor. data from the recipe end processor to a memory location of its own choosing. In starting the block transfer, which is a high-speed transfer protocol for tab blocks, , which acts as a master processor.

In transferring the message descriptor from the sender to the recipe end, the recipe end Processor FIFO is full, message descriptor write operation If the input is successful, the recipe end control logic sends a DTACK* signal. A 1030° sender that responds to the transfer of a message descriptor by sending If the FIFO written by is full, 1020, recipe end control theory The logic circuit detects a bus error, that is, a message by driving BERR* low. Indicates a bus lock on a descriptor write operation. This will cause the sender to It is reported that the site operation was unsuccessful. The sender is again Wait 1050 for a specified time interval before attempting a write operation. The waiting time is determined by the field of use. After waiting the specified time, 1050, se The reader will try the write operation again! 01.0. This step The sage descriptor transfer operation is successful (i.e., the sender or BERR* DTACK* is received).

FIG. 13 is a block diagram of a bus-locking multiprocessor communication system. . Each of processor 1101 and processor 1103 is connected to VME bus 22. It is continued. Message description for both processors 1101 and +103 children can be sent and received on the VME bus 22.

The message descriptor is the sender, e.g. 1101. Recipe End by, analogy For example, it is transmitted to FIFO 1103 via the VME bus. Start the transfer Therefore, the sender's microprocessor 1140 stores the descriptor and its address. are typically broadcast one word at a time via VME bus 22. sender The address broadcast by corresponds to the bus address of the FIFO at the end of the recipe. do. If the FIFO is empty or not full, the message Descriptors are received and stored by FIFO 1120. microprocessor - When the 1140 is ready to process the next message descriptor, the microprocessor The processor 1140 reads the message descriptor from the FIFO 1120. can.

If the recipe end FIFO 01120 is full, the FIFO 1120 IFO filling line! 25 to the FIFO filling signal to the recipe end control logic. to circuit 1130. Recipe end control logic according to FIFO full signal Circuit 1130 sets BERR* signal to BERR main signal line 112 - It occurs because of this.

FIG. 14 shows the features of a bus-locking multiprocessor communication system according to the present invention. 1 is a block diagram of one preferred embodiment of a message transfer unit; FIG. message description The child is routed through the VME bus 22 to a sender processor not shown in FIG. Therefore, the data is sent to the recipe end processor by the data receiving unit 1210. received. Similarly, addresses and address modifiers, VMEbus 2 2 by the sender processor and received by the address receiver 1240. The received address is passed to the bear address detection circuit 1250. The address detection circuit detect address and address modifier and enable control logic 1130 . Addresses and addresses sent by sender processors not shown in Figure 14 and address modifier by lines 1247 and 1245, respectively. Provided to control logic circuit 1130. The sent address is FIFO11 20 is specified as the intended recipe end.

FIFO 1120 is a conventional FIFO with at least three data storage states. i.e. all FIFO storage locations are full and no further data can be stored. ``FIFO full'' condition indicating that there is no message descriptor in memory, but not all “FIFO not full” status indicating that a certain memory storage location is available; “F” indicates that all memory locations are available for storing message descriptors. ■FO is in a blank state.

FIF01120 is a FIF○ charging signal interconnected to control logic circuit 1130. Full signal Squid line 1125. A “FIFO full” condition exists and the sender process When a server attempts to write descriptor data to a full FIFO 1120, the FIFO FO charging <Learn+'> l l l 25c, FIFO1120i: Therefore, it is activated. Ru. The FIFO blank signal line 1235 is connected to the control microprocessor sensor 1220. If connected and microprocessor-1220 FIFO II20 or empty ,Notice.

FIFO non-blank signal line 1236 indicates that the message descriptor is in FIFO 1120. The control process determines that it exists in some memory location or not in all memory locations. the control processor 1220 for communicating with the processor 1220; .

A data input line 1215 connects the data receiving section 1210 and the FIFO 1120. Continue. Data is transferred from FIF01120 to control processor 1220. It is output through input 1233. Two control lines to control logic circuit 1130 To the connected FIFO light 123L and microprocessor-1220 The connected FIFO lead 1237 is connected to the FIFO 1120 or to the FIFO lead 1237. Controls the flow of data from FO1120.

WRITE* signal line 1127 connects the microprocessor-1220 and control logic. The circuit 1130 is connected and the microprocessor 1220 performs a data write operation. It is driven low when the application is desired to be activated. Data line 1129 The microprocessor 1220 and the data transmitting/receiving section 1212 are connected. similar , address line! ! 23 and address modifier line 1122 are micro The processor 1220 and address transmitting/receiving section 1213 are connected. data sending The receiving unit 1212 receives data to and from the VME bus 22, respectively. is transmitting or receiving. Similarly, the address transmitting/receiving unit 1213 Addresses and address modifiers to the E bus 22 or from the VME bus 22 , are sending or receiving, respectively.

Control logic circuit 1130 includes WRITE* line 1250, BERR* line 12 62, DTACK* line 1264 and DSO*1266 22. WRITlj line 1250, DTACK* line 12 64 and DS(l lines operate as described. If successful, the recipe end processor sends DTA CK to control logic circuit 1130. It responds to the transfer by causing * to go low.

F　If IFOfull status exists, if the sender's processor or [J Although not shown in Figure 14, an attempt is made to write a message descriptor to FIFO 1120. The FIFO then activates the FIFO fill line 1125.

As soon as the FIFO fill signal is received through the fill line +125, the control logic line 1130 drives BERR* line 1250 low, thereby inform the reader that the write operation was unsuccessful. BERR *As soon as the signal is received, the sender must resend the descriptor to the recipe end. and select.

If the FIFO is not full and the write operation is successful, the message The descriptor is used for subsequent access and processing by the recipe end microprocessor-1220. stored in FIFO 1120 for further use. Recipe end processor control The message descriptor is activated by the DTACK* signal generated by the control logic circuit 1130. transfer has been successfully completed.

The processor system shown in Figure 14 is also used for sending message descriptors. It is possible to use Recipe end processor not shown in Figure 14 To send a message descriptor on the VME bus 22 to The processor 1220 converts the message data to be transferred into ``message data''. - Compile into “” format.The address and address of the intended recipe end FIFO. The address modifier is sent to address transceiver +213. microprocessor -1220 drives the WRITE line 112. In response to this , control logic 1130 controls the process by driving the WRIT]lj line low. indicates that the server has started a write operation. The message descriptor is a pointer to a “message descriptor” or a microprocessor -1220, it is transmitted to the data transmitting/receiving section 1212. data, address and address modifiers are broadcast onto the VME bus 22 by their respective transceivers. sent. As described, if the addressed FIFO is full, the processor received a BERR* signal, indicating that the light operating controller was unsuccessful. Show that.

The detailed description of the invention sets forth merely preferred embodiments. All of the above Modifications and variations of the invention may be made without departing from the spirit and scope of the invention and the claims. enter. Other features, objects and advantages of the invention will be found in the drawings, description and appended claims. The scope of this will become clearer.

FIG.-3 DSO’ & DS1” 1-1 + 24-3÷-4÷←1→←2→←3→DTACK' D.S.O.” )-1+　2-4-1-- IITACK” FIG, -4B Engraving (no changes to the content) DτACK' - Ding One Eleven - FIG, -5B Engraving (no changes to the content) DTACK” Data Valid data Pure i! (No change in content) Engraving (no changes to the content) FIG, -7B Engraving (contents + no changes) Engraving (no changes to the content) FIG, -8A ξ (no change) Engraving (no changes to the content) Engraving (no change in content) Heisei Year Month Day

Claims (4)

[Claims] 1. Message from master processor to slave processor via VME bus A message transfer system for transferring message data, wherein the master process the VM for receiving and storing the message data transferred from the server; FIFO means connected to the E bus and said FIFO means are connected to said FIFO hand. FIFO full condition indicating that the stage is unable to store message data and the FIFO has a FIFO full signal indicating the existence of the FIFO full condition. Occurred; in response to receiving a FIFO full signal from said FIFO means. said FIFO means and said VME bus for transmitting a bus error signal when and means connected to. 2. Message from master processor to slave processor via VME bus A message transfer system for transferring message data, wherein the master process A message data channel that receives message data sent from a server. and the message data channel means are connected to the VME bus. hand; connected to said message channel means for storing message data; FIFO means; and the FIFO means is configured to receive message data by the FIFO means. has a FIFO full status indicating that it cannot be stored; generating a FIFO full signal indicating the existence of the FIFO full condition; bus error through the VME bus in response to receiving a FIFO full signal from the VME bus. and means for transmitting a signal. 3. Mechanisms are transferred from the master processor to the slave processors via the VME bus. The message data transfer is performed by the slave processor to transfer the message data. If the thread data cannot be memorized, there is a way to stop the thread. A FIFO means connected to a memory processor is provided through the VME bus to the FIFO means connected to the memory processor. activating a write cycle to write the message data; Indicates that the IFO means is unable to collect transmitted message data. to send a bus error in response to a write cycle initiation. A method characterized by comprising: 4. additionally restarting said light cycle after a preset time interval; 4. The method of claim 3, further comprising the steps of: