KR920020690A - Semiconductor lead frame - Google Patents

Semiconductor lead frame Download PDF

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Publication number
KR920020690A
KR920020690A KR1019910006291A KR910006291A KR920020690A KR 920020690 A KR920020690 A KR 920020690A KR 1019910006291 A KR1019910006291 A KR 1019910006291A KR 910006291 A KR910006291 A KR 910006291A KR 920020690 A KR920020690 A KR 920020690A
Authority
KR
South Korea
Prior art keywords
lead frame
lead
chip
adhesive tape
semiconductor lead
Prior art date
Application number
KR1019910006291A
Other languages
Korean (ko)
Other versions
KR940002389B1 (en
Inventor
오세혁
정하천
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910006291A priority Critical patent/KR940002389B1/en
Priority to JP4060294A priority patent/JPH05102388A/en
Publication of KR920020690A publication Critical patent/KR920020690A/en
Application granted granted Critical
Publication of KR940002389B1 publication Critical patent/KR940002389B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

내용 없음No content

Description

반도체 리이드 프레임Semiconductor lead frame

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 이 발명에 따른 반도체 리이드 프레임 구조도.4 is a structure diagram of a semiconductor lead frame according to the present invention.

제5도는 제4도의 A부 상세도.5 is a detailed view of portion A of FIG.

제6도는 이 발명의 와이어 본딩 공정의 클램핑 상태도.6 is a clamping state diagram of the wire bonding process of the present invention.

제7도는 이 발명의 봉지수지 주입 공정 상태도이다.7 is a state diagram of the encapsulating resin injection process of the present invention.

Claims (1)

사각모서리가 서포트바에 의해 지지되고 상면에 칩이 부착되는 리이드 프레임 패드와, 상기 리이드 프레임패드의 사방으로 배열 형성되어 칩과 와이어 본딩되는 리이드와, 상기 리이드의 변형을 방지하도록 부착된 접착테이프로 이루어진 반도체 리이드 프레임에 있어서, 상기 칩과 와이어 본딩되는 리이드의 팁부위 저면에 접착테이프가 접착되고, 상기 접착테이프가 접착되지 않은 부위의 리이드가 서포트비를 중심으로 하여 바깥쪽으로 절곡되어 공간부가 형성되며, 서포트바로 지지되는 리이드 프레임 패드의 사각모서리부 및 가장자리에 경사면과 홈들을 형성하여 됨을 특징으로 하는 반도체 리이드 프레임.A lead frame pad supported by a support bar and attached to a chip on an upper surface thereof, a lead arranged in all directions of the lead frame pad to bond the wire to the chip, and an adhesive tape attached to prevent deformation of the lead In the semiconductor lead frame, an adhesive tape is adhered to the bottom surface of the tip of the lead bonded to the chip, and the lead of the portion where the adhesive tape is not bonded is bent outwardly around the support ratio to form a space portion. A semiconductor lead frame, characterized in that the inclined surface and the grooves are formed in the square corner portion and the edge of the lead frame pad supported by the support bar. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910006291A 1991-04-19 1991-04-19 Semiconductor leadframe KR940002389B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910006291A KR940002389B1 (en) 1991-04-19 1991-04-19 Semiconductor leadframe
JP4060294A JPH05102388A (en) 1991-04-19 1992-03-17 Semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910006291A KR940002389B1 (en) 1991-04-19 1991-04-19 Semiconductor leadframe

Publications (2)

Publication Number Publication Date
KR920020690A true KR920020690A (en) 1992-11-21
KR940002389B1 KR940002389B1 (en) 1994-03-24

Family

ID=19313461

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006291A KR940002389B1 (en) 1991-04-19 1991-04-19 Semiconductor leadframe

Country Status (2)

Country Link
JP (1) JPH05102388A (en)
KR (1) KR940002389B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998043288A1 (en) * 1997-03-24 1998-10-01 Seiko Epson Corporation Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JPH05102388A (en) 1993-04-23
KR940002389B1 (en) 1994-03-24

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