KR980006166A - Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same - Google Patents

Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same Download PDF

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Publication number
KR980006166A
KR980006166A KR1019960020910A KR19960020910A KR980006166A KR 980006166 A KR980006166 A KR 980006166A KR 1019960020910 A KR1019960020910 A KR 1019960020910A KR 19960020910 A KR19960020910 A KR 19960020910A KR 980006166 A KR980006166 A KR 980006166A
Authority
KR
South Korea
Prior art keywords
lead
chip
groove
inner lead
semiconductor chip
Prior art date
Application number
KR1019960020910A
Other languages
Korean (ko)
Inventor
김태형
박태성
최희국
Original Assignee
김광호
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자주식회사 filed Critical 김광호
Priority to KR1019960020910A priority Critical patent/KR980006166A/en
Publication of KR980006166A publication Critical patent/KR980006166A/en

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Abstract

본 발명은 리드 온 칩용 리드프레임 및 그를 이용한 반도체 칩 패키지에 관한 것으로, 비전도성 접착제가 접착되어 있지 않은 부분의 내부리드에 홈을 형성함으로써, 성형수지의 흐름을 일정하게 유지하여 내부리드와 칩사이에서 보이드가 발생되는 것을 억제할 수 있는 장점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a lead-on chip and a semiconductor chip package using the same, wherein a groove is formed in an inner lead of a portion to which a non-conductive adhesive is not bonded, thereby maintaining a constant flow of the molding resin, and thus between the inner lead and the chip There is an advantage that can suppress the generation of voids.

Description

내부리드에 홈이 형성된 리드 온 칩용 리드프레임 및 그를 이용한 반도체 칩 패키지Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 일실시예에 의한 내부리드 하부면에 홈이 형성된 상태를 나타내는 리드온 칩 패키지의 부분 절개도.3 is a partial cutaway view of a lead-on chip package showing a state in which a groove is formed in a lower surface of an inner lead according to an embodiment of the present invention.

Claims (6)

칩 상부면에 비전도성 접착제에 의해 접착될 내부리드들과; 그 내부리드들과 일체형으로 형성된 외부리드들을 갖는 리드 온 칩용 리드프레임에 있어서, 상기 접착제가 접착되지 않는 상기 내부리드의 부분에 홈이 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임.Inner leads to be bonded to the chip upper surface by a non-conductive adhesive; A lead frame for a lead-on chip having a lead on chip having an inner lead formed integrally with the inner leads, wherein the groove is formed in a portion of the inner lead to which the adhesive is not bonded. . 제1항에 있어서, 상기 홈이 상기 내부리드의 하부면에 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임.The lead frame according to claim 1, wherein the groove is formed on the lower surface of the inner lead. 제1항에 있어서, 상기 홈이 상기내부리드의 상부면에 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임.The lead frame according to claim 1, wherein the groove is formed on the upper surface of the inner lead. 상부면에 복수개의 본딩패드들을 갖는 칩과; 상기 칩의 상부면에 비전도성 접착제에 의해 접착되어 있으며, 상기 본딩패드들과 각기 대응되어 전기적으로 연결된 내부리드들과, 그 내부리드들과 일체형으로 형성된 외부리드들을 갖는 리드 온 칩용 리드프레임과; 상기 칩과 내부리드들을 보호하기 위해 내재ㆍ봉지하는 성형수지;를 포함하는 리드 온 칩 패키지에 있어서, 상기 비전도성 접착제가 접착되지 않는 상기 내부리드의 부분에 홈이 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임을 이용한 반도체 칩 패키지.A chip having a plurality of bonding pads on an upper surface thereof; A lead frame for a lead-on chip bonded to an upper surface of the chip by a non-conductive adhesive and having inner leads electrically connected to the bonding pads, respectively, and having outer leads integrally formed with the inner leads; In the lead-on chip package comprising a molded resin that is embedded and sealed to protect the chip and the inner lead, the inner lead, characterized in that the groove is formed in the portion of the inner lead to which the non-conductive adhesive is not bonded A semiconductor chip package using a lead frame for grooved lead-on chips. 제4항에 있어서, 상기 홈이 내부리드의 하부면에 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임을 이용한 반도체 칩 패키지.5. The semiconductor chip package of claim 4, wherein the groove is formed on a lower surface of the inner lead. 6. 제4항에 있어서, 상기 홈이 내부리드의 상부면에 형성된 것을 특징으로 하는 내부리드에 홈이 형성된 리드 온 칩용 리드프레임을 이용한 반도체 칩 패키지.5. The semiconductor chip package of claim 4, wherein the groove is formed on an upper surface of the inner lead. 6.
KR1019960020910A 1996-06-12 1996-06-12 Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same KR980006166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960020910A KR980006166A (en) 1996-06-12 1996-06-12 Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960020910A KR980006166A (en) 1996-06-12 1996-06-12 Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same

Publications (1)

Publication Number Publication Date
KR980006166A true KR980006166A (en) 1998-03-30

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KR1019960020910A KR980006166A (en) 1996-06-12 1996-06-12 Lead frame for lead-on chip with groove formed in inner lead and semiconductor chip package using same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100610955B1 (en) * 2000-12-26 2006-08-10 앰코 테크놀로지 코리아 주식회사 Leadframe for semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100610955B1 (en) * 2000-12-26 2006-08-10 앰코 테크놀로지 코리아 주식회사 Leadframe for semiconductor package

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