KR960043142A - Semiconductor leadframe - Google Patents

Semiconductor leadframe Download PDF

Info

Publication number
KR960043142A
KR960043142A KR1019950012120A KR19950012120A KR960043142A KR 960043142 A KR960043142 A KR 960043142A KR 1019950012120 A KR1019950012120 A KR 1019950012120A KR 19950012120 A KR19950012120 A KR 19950012120A KR 960043142 A KR960043142 A KR 960043142A
Authority
KR
South Korea
Prior art keywords
chip
tape
semiconductor
support bar
lead frame
Prior art date
Application number
KR1019950012120A
Other languages
Korean (ko)
Other versions
KR0147638B1 (en
Inventor
황규성
김기수
Original Assignee
이대원
삼성항공산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이대원, 삼성항공산업 주식회사 filed Critical 이대원
Priority to KR1019950012120A priority Critical patent/KR0147638B1/en
Publication of KR960043142A publication Critical patent/KR960043142A/en
Application granted granted Critical
Publication of KR0147638B1 publication Critical patent/KR0147638B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

반도체 리드프레임에 관하여 개시되어 있다.Disclosed is a semiconductor leadframe.

종래의 테이프 접착 방식의 반도체 리드프레임에 있어서는 테이프의 소요량이 많아 그 적용이 제한되어 있었으나, 본 발명에 의한 반도체 리드프레임은 패드를 제거하고 서포트 바의 양 끝단 부근에 칩의 상하(또는 좌우)와 접착되는 막대모양의 칩 접착부를 만들어 테이프를 막대 모양으로 절단하여 접착함으로써 그 소요량을 줄여 원가를 절감하는 동시에 패키지의 신뢰성을 향상하도록 한 것이다.In the conventional tape-bonding semiconductor lead frame, the tape requirement is large and its application is limited. However, in the semiconductor lead frame according to the present invention, the pads are removed, and the top and bottom (or left and right) of the chip are placed near both ends of the support bar. By making the stick-shaped chip-bonded portion to be bonded, the tape is cut and adhered to the shape of a rod to reduce the required amount of cost and to improve the reliability of the package.

Description

반도체 리드프레임Semiconductor leadframe

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 반도체 리드프레임의 개략적 평면도이다, 제3도는 본 발명에 따른 반도체 리드프레임의 접착부를 나타내는 부분도이다.2 is a schematic plan view of a semiconductor lead frame according to the present invention, and FIG. 3 is a partial view showing an adhesive portion of the semiconductor lead frame according to the present invention.

Claims (2)

서포트 바의 양 끝단에 칩의 상하(또는 좌우)와 접착되는 칩접착부가 구비되고, 양면 접착테이프에 의해 상기 칩 접착부에 칩이 접착되는 것을 특징으로 하는 반도체 리드프레임.A chip lead portion is provided at both ends of the support bar, the chip adhesive portion adhering to the upper and lower sides (or left and right sides) of the chip, and the chip is attached to the chip bonding portion by a double-sided adhesive tape. 제1항에 있어서, 상기 서포드 바에 수직으로 연결되는 막대 모양의 평면 칩 접착부를 가지는 것을 특징으로 하는 반도체 리드프레임.The semiconductor leadframe of claim 1, further comprising a bar-shaped planar chip adhesive part vertically connected to the support bar. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012120A 1995-05-16 1995-05-16 Semiconductor lead frame KR0147638B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950012120A KR0147638B1 (en) 1995-05-16 1995-05-16 Semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950012120A KR0147638B1 (en) 1995-05-16 1995-05-16 Semiconductor lead frame

Publications (2)

Publication Number Publication Date
KR960043142A true KR960043142A (en) 1996-12-23
KR0147638B1 KR0147638B1 (en) 1998-08-01

Family

ID=19414608

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950012120A KR0147638B1 (en) 1995-05-16 1995-05-16 Semiconductor lead frame

Country Status (1)

Country Link
KR (1) KR0147638B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100384079B1 (en) * 1999-11-01 2003-05-14 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100384079B1 (en) * 1999-11-01 2003-05-14 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Also Published As

Publication number Publication date
KR0147638B1 (en) 1998-08-01

Similar Documents

Publication Publication Date Title
KR880011939A (en) Assembly method of semiconductor laser
KR910001956A (en) Semiconductor device
KR960043142A (en) Semiconductor leadframe
KR940016723A (en) Semiconductor lead frame
KR910010686A (en) Resin Sealed Semiconductor Device
KR960019678A (en) How to attach heat sink and lead frame of semiconductor package
KR920020690A (en) Semiconductor lead frame
KR970024101A (en) Lead frame with internal leads installed in the slit of the die pad
KR920001686A (en) Package structure using two-step bonding
KR970023896A (en) Semiconductor Chip Package Without Die Bonding Layer
KR970024083A (en) Lead frame with adhesive film attached to the die pad.
KR970053740A (en) Leadframe with Improved Die Pad
KR970024031A (en) Lead On Chip Package With Multiple Semiconductor Chips
KR960043143A (en) Lead Frames for Semiconductor Packages
KR970023917A (en) Semiconductor package to prevent short circuit of wire
KR960035996A (en) Chip Holding Lead-on Chip Type Semiconductor Package
KR920022483A (en) MCPs for semiconductor devices with optical windows
KR960019671A (en) Lead-on-Chip Package
KR970024084A (en) Semiconductor Chip Package Using Substrate Pads
KR970024113A (en) Lead-on chip package manufacturing method
KR920013676A (en) Assembly method of semiconductor device with optical window
KR910010680A (en) Leadframe Pads for Semiconductor Components
KR970013260A (en) Lead frame for lead-on chip with index part for preventing displacement of chip
KR970018429A (en) Packing structure in which die pad is adhered on active area of chip and package using the structure
KR960005958A (en) Semiconductor Package

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100426

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee