KR920010788A - 고저항용 다결정 실리콘의 저항치 유지방법 - Google Patents

고저항용 다결정 실리콘의 저항치 유지방법 Download PDF

Info

Publication number
KR920010788A
KR920010788A KR1019900019326A KR900019326A KR920010788A KR 920010788 A KR920010788 A KR 920010788A KR 1019900019326 A KR1019900019326 A KR 1019900019326A KR 900019326 A KR900019326 A KR 900019326A KR 920010788 A KR920010788 A KR 920010788A
Authority
KR
South Korea
Prior art keywords
heat treatment
resistance
polycrystalline silicon
atmosphere
protective layer
Prior art date
Application number
KR1019900019326A
Other languages
English (en)
Other versions
KR930009549B1 (ko
Inventor
하형찬
김정태
백용구
천희곤
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019900019326A priority Critical patent/KR930009549B1/ko
Priority to US07/797,994 priority patent/US5212119A/en
Priority to JP3314903A priority patent/JPH04299566A/ja
Publication of KR920010788A publication Critical patent/KR920010788A/ko
Application granted granted Critical
Publication of KR930009549B1 publication Critical patent/KR930009549B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

고저항용 다결정 실리콘의 저항치 유지방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 스태틱램의 회로도,
제2도는 본 발명의 제1실시예에 의해 다결정 실리콘의 저항치 증감을 도시한 그래프도.

Claims (6)

  1. 반도체 소자내에 고정항 다결정 실리콘이 형성되고 그 상부에 보호층으로 실리콘 산화막과 실리콘 질화막을 플라즈마 화학 증착법을 이용하여 형성할 때 하부의 고저항 다결정 실리콘에 차아지(charge)를 갖는 이온 및 전자들이 침투되어 저항치가 떨어지는 것을 방지하기 위하여, 실리콘 산화막 및 실리콘 질화막으로 된 보호층을 플라즈마 화학 증착법을 이용하여 소정의 두께로 형성한 다음, O2플라즈마 상태에서 열처리한다음, N2분위기에서 열처리하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
  2. 제1항에 있어서, O2플라즈마 상태에서 열처리는 산소유량 500∼1000SSCM, 전력 300∼500W, 13.56MHz 라디오 주파수(Radio frequency)를 인가하고, 300∼400℃에서 1∼2분정도 열처리하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
  3. 제1항에 있어서, 상기 N2분위기에서 열처리하는 것은 N2분위기내에 350∼450℃에서 30∼60분 정도 열처리하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
  4. 반도체 소자내에 고정항 다결정 실리콘이 형성되고 그 상부에 보호층으로 실리콘 산화막과 실리콘 질화막을 플라즈마 화학증착법을 이용하여 형성할때 하부의 고저항 다결정 실리콘에 차아지를 갖는 이온 및 전자들이 침투되어 저항치가 떨어지는 것을 방지하고 오히려 저항치가 증가되도록 하기 위하여, 보호층으로 1차 실리콘 산화막을 소정두께 형성하고 O2플라즈마 상태에서 열처리와 N2분위기에서 열처리하는 각각 실시한 다음, 보호층으로 2차 실리콘 질화막을 소정두께 형성하고 O2플라즈마 상태에서 열처리와 N2분위기에서 열처리를 각각 실시하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
  5. 제4항에 있어서, 상기 O2플라즈마 상태에서 열처리는 산소유량 500∼1000SSCM, 전력 300∼500W, 13.56MHz 라디오 주파수를 인가하고, 300∼400℃에서 1∼2분정도 열처리하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
  6. 제4항에 있어서, 상기 N2분위기에서 열처리하는 것은 N2분위기내에 350∼450℃에서 30∼60분 정도 열처리하는 것을 특징으로 하는 고저항용 다결정 실리콘의 저항치 유지방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019900019326A 1990-11-28 1990-11-28 고저항용 다결정 실리콘의 저항치 유지방법 KR930009549B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019900019326A KR930009549B1 (ko) 1990-11-28 1990-11-28 고저항용 다결정 실리콘의 저항치 유지방법
US07/797,994 US5212119A (en) 1990-11-28 1991-11-26 Method for maintaining the resistance of a high resistive polysilicon layer for a semiconductor device
JP3314903A JPH04299566A (ja) 1990-11-28 1991-11-28 高抵抗用多結晶シリコンの抵抗値維持方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900019326A KR930009549B1 (ko) 1990-11-28 1990-11-28 고저항용 다결정 실리콘의 저항치 유지방법

Publications (2)

Publication Number Publication Date
KR920010788A true KR920010788A (ko) 1992-06-27
KR930009549B1 KR930009549B1 (ko) 1993-10-06

Family

ID=19306629

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900019326A KR930009549B1 (ko) 1990-11-28 1990-11-28 고저항용 다결정 실리콘의 저항치 유지방법

Country Status (3)

Country Link
US (1) US5212119A (ko)
JP (1) JPH04299566A (ko)
KR (1) KR930009549B1 (ko)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100287952B1 (ko) * 1993-10-01 2001-12-28 야마자끼 순페이 반도체장치제작방법
KR100695004B1 (ko) * 2005-11-01 2007-03-13 주식회사 하이닉스반도체 반도체 소자의 산화막 형성 방법
KR101350048B1 (ko) * 2012-01-05 2014-01-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 더미 게이트를 제거한 집적회로 저항기 제조
US9666614B2 (en) 2002-04-09 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10527903B2 (en) 2002-05-17 2020-01-07 Semiconductor Energy Laboratory Co., Ltd. Display device
US10700106B2 (en) 2002-04-09 2020-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814529A (en) 1995-01-17 1998-09-29 Semiconductor Energy Laboratory Co., Ltd. Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
JPH0955381A (ja) * 1995-08-11 1997-02-25 S I I R D Center:Kk 半導体集積回路の製造方法
US6489213B1 (en) * 1996-01-05 2002-12-03 Integrated Device Technology, Inc. Method for manufacturing semiconductor device containing a silicon-rich layer
US6096645A (en) * 1997-07-24 2000-08-01 Mosel Vitelic, Inc. Method of making IC devices having stable CVD titanium nitride films
US5976990A (en) * 1998-01-09 1999-11-02 Micron Technology, Inc. Method for optimization of thin film deposition
JP2994616B2 (ja) 1998-02-12 1999-12-27 キヤノン販売株式会社 下地表面改質方法及び半導体装置の製造方法
US6511921B1 (en) * 1999-01-12 2003-01-28 Sumco Phoenix Corporation Methods for reducing the reactivity of a semiconductor substrate surface and for evaluating electrical properties of a semiconductor substrate
US6900138B1 (en) * 1999-03-01 2005-05-31 Micron Technology, Inc. Oxygen plasma treatment for nitride surface to reduce photo footing
US7411215B2 (en) * 2002-04-15 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
JP3989763B2 (ja) 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
US8980382B2 (en) 2009-12-02 2015-03-17 Applied Materials, Inc. Oxygen-doping for non-carbon radical-component CVD films
US8741788B2 (en) 2009-08-06 2014-06-03 Applied Materials, Inc. Formation of silicon oxide using non-carbon flowable CVD processes
US20110136347A1 (en) * 2009-10-21 2011-06-09 Applied Materials, Inc. Point-of-use silylamine generation
US8449942B2 (en) 2009-11-12 2013-05-28 Applied Materials, Inc. Methods of curing non-carbon flowable CVD films
US20110159213A1 (en) * 2009-12-30 2011-06-30 Applied Materials, Inc. Chemical vapor deposition improvements through radical-component modification
JP2013516763A (ja) * 2009-12-30 2013-05-13 アプライド マテリアルズ インコーポレイテッド フレキシブルな窒素／水素比を使用して生成されるラジカルを用いる誘電体膜成長
CN102754193A (zh) * 2010-01-06 2012-10-24 应用材料公司 使用氧化物衬垫的可流动电介质
JP2013521650A (ja) 2010-03-05 2013-06-10 アプライド マテリアルズ インコーポレイテッド ラジカル成分ｃｖｄによる共形層
US9285168B2 (en) 2010-10-05 2016-03-15 Applied Materials, Inc. Module for ozone cure and post-cure moisture treatment
US8664127B2 (en) 2010-10-15 2014-03-04 Applied Materials, Inc. Two silicon-containing precursors for gapfill enhancing dielectric liner
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8450191B2 (en) 2011-01-24 2013-05-28 Applied Materials, Inc. Polysilicon films by HDP-CVD
US8716154B2 (en) 2011-03-04 2014-05-06 Applied Materials, Inc. Reduced pattern loading using silicon oxide multi-layers
US20120238108A1 (en) * 2011-03-14 2012-09-20 Applied Materials, Inc. Two-stage ozone cure for dielectric films
US8445078B2 (en) 2011-04-20 2013-05-21 Applied Materials, Inc. Low temperature silicon oxide conversion
US8466073B2 (en) 2011-06-03 2013-06-18 Applied Materials, Inc. Capping layer for reduced outgassing
US9404178B2 (en) 2011-07-15 2016-08-02 Applied Materials, Inc. Surface treatment and deposition for reduced outgassing
US8617989B2 (en) 2011-09-26 2013-12-31 Applied Materials, Inc. Liner property improvement
US8551891B2 (en) 2011-10-04 2013-10-08 Applied Materials, Inc. Remote plasma burn-in
US8889566B2 (en) 2012-09-11 2014-11-18 Applied Materials, Inc. Low cost flowable dielectric films
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films
US9412581B2 (en) 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US10211326B2 (en) * 2016-03-31 2019-02-19 Stmicroelectronics (Tours) Sas Vertical power component

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2967704D1 (de) * 1978-06-14 1991-06-13 Fujitsu Ltd Verfahren zur herstellung einer halbleiteranordnung mit einer isolierschicht.
JPS6060752A (ja) * 1983-09-14 1985-04-08 Oki Electric Ind Co Ltd 高抵抗ポリシリコンの製造方法
US4742020A (en) * 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
JPS621237A (ja) * 1985-06-27 1987-01-07 Toshiba Corp 多結晶質膜の製造方法
US4774202A (en) * 1985-11-07 1988-09-27 Sprague Electric Company Memory device with interconnected polysilicon layers and method for making
KR910003742B1 (ko) * 1986-09-09 1991-06-10 세미콘덕터 에너지 라보라터리 캄파니 리미티드 Cvd장치
US4882299A (en) * 1987-07-16 1989-11-21 Texas Instruments Incorporated Deposition of polysilicon using a remote plasma and in situ generation of UV light.
US4897360A (en) * 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
JPH0258266A (ja) * 1988-08-23 1990-02-27 Sony Corp 半導体メモリ装置の製造方法
JP2708899B2 (ja) * 1989-07-27 1998-02-04 三洋電機株式会社 多結晶薄膜の表面処理方法
JP3029434B2 (ja) * 1989-12-29 2000-04-04 正俊 右高 絶縁膜の製造方法及びこの絶縁膜を使用する半導体装置の製造方法
US4981811A (en) * 1990-04-12 1991-01-01 At&T Bell Laboratories Process for fabricating low defect polysilicon
JPH0439931A (ja) * 1990-06-06 1992-02-10 Oki Electric Ind Co Ltd 半導体装置の酸化膜形成方法
JPH0496216A (ja) * 1990-08-04 1992-03-27 Tonen Corp 多結晶膜の作製法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100287952B1 (ko) * 1993-10-01 2001-12-28 야마자끼 순페이 반도체장치제작방법
US6335555B1 (en) 1993-10-01 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a manufacturing method for the same
KR100332619B1 (ko) * 1993-10-01 2002-04-15 야마자끼 순페이 박막트랜지스터
US6835607B2 (en) 1993-10-01 2004-12-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method for manufacturing the same
US9666614B2 (en) 2002-04-09 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10700106B2 (en) 2002-04-09 2020-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US10854642B2 (en) 2002-04-09 2020-12-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US11101299B2 (en) 2002-04-09 2021-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10527903B2 (en) 2002-05-17 2020-01-07 Semiconductor Energy Laboratory Co., Ltd. Display device
US11422423B2 (en) 2002-05-17 2022-08-23 Semiconductor Energy Laboratory Co., Ltd. Display device
KR100695004B1 (ko) * 2005-11-01 2007-03-13 주식회사 하이닉스반도체 반도체 소자의 산화막 형성 방법
KR101350048B1 (ko) * 2012-01-05 2014-01-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 더미 게이트를 제거한 집적회로 저항기 제조

Also Published As

Publication number Publication date
US5212119A (en) 1993-05-18
KR930009549B1 (ko) 1993-10-06
JPH04299566A (ja) 1992-10-22

Similar Documents

Publication Publication Date Title
KR920010788A (ko) 고저항용 다결정 실리콘의 저항치 유지방법
US5861651A (en) Field effect devices and capacitors with improved thin film dielectrics and method for making same
US4640004A (en) Method and structure for inhibiting dopant out-diffusion
US6380056B1 (en) Lightly nitridation surface for preparing thin-gate oxides
JPS5748246A (en) Manufacture of semiconductor device
US3660735A (en) Complementary metal insulator silicon transistor pairs
JPS5932172A (ja) シヨツトキ−障壁ｍｏｓデバイスからなる集積回路及びその製造方法
JPS60109260A (ja) 補償された多結晶シリコン抵抗素子
US3550256A (en) Control of surface inversion of p- and n-type silicon using dense dielectrics
US5773339A (en) Method of making diffused layer resistors for semiconductor devices
KR950027916A (ko) 반도체장치의 제조방법
JPS571252A (en) Semiconductor device
JPS5512752A (en) Semiconductor device manufacturing method
US5418184A (en) Method of manufacturing a semiconductor device in which dopant atoms are provided in a semiconductor body
JPS5933255B2 (ja) 半導体装置の製造方法
KR100256246B1 (ko) 반도체 소자의 게이트 전극 형성 방법
KR950030336A (ko) 캐패시터의 유전체막 형성방법
KR0170338B1 (ko) 반도체 장치의 게이트 패턴 형성방법
KR100332124B1 (ko) 반도체소자의게이트전극형성방법
KR940010234A (ko) 반도체 장치의 제조 방법
Topich Compensation of mobile‐ion movement in SiO2 by ion implantation
JPS55105380A (en) Manufacture of semiconductor device
RU1145838C (ru) Способ изготовлени ВЧ-транзисторных структур
KR940011799B1 (ko) TiN층으로 된 전하저장전극 형성방법
JPH0673349B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090922

Year of fee payment: 17

EXPY Expiration of term