KR920001334A - 멀티프로세서 또는 파이프 라인식 프로세서 시스템에서 데이타의 보존을 확실히 하는 방법 - Google Patents

멀티프로세서 또는 파이프 라인식 프로세서 시스템에서 데이타의 보존을 확실히 하는 방법 Download PDF

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KR920001334A
KR920001334A KR1019910010878A KR910010878A KR920001334A KR 920001334 A KR920001334 A KR 920001334A KR 1019910010878 A KR1019910010878 A KR 1019910010878A KR 910010878 A KR910010878 A KR 910010878A KR 920001334 A KR920001334 A KR 920001334A
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providing
external memory
byte
memory location
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KR1019910010878A
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KR0185988B1 (ko
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리챠드 엘. 사이트스
리챠드 티. 위테크
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원본미기재
디지탈 이큅먼트 코오포레이숀
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음

Description

멀티프로세서 또는 파이프 라인식 프로세서 시스템에서 데이타의 보존을 확실히 하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 특징을 이용할 수 있는 CPU를 채용한 컴퓨터 시스템의 전기 블록도,
제2도는 제1도의 프로세서에 사용되는 데이타 형태에 관한 도면.

Claims (11)

  1. 프로세서의 동작중에 아토믹 바이트의 기입을 수행하는 방법에 있어서, 선택적으로 정렬된 바이트의 외부 메모리 위치의 내용을 내부 레지스터수단에 로드한 다음 상기 선택된 외부 메모리 위치에 대한 임의의 다른 기억부를 검출하는 단계를 포함하는데, 상기 내용은 기입 되는 비정렬 바이트 위치를 포함하며; 상기 선택된 외부 메모리 위치에 임의의 다른 기억부가 구성되어 있는 가의 표시를 제공하는 단계와; 상기 내부 레지스터 수단에 상기 비정렬된 바이트위치의 값을 기입될 새로운 값으로 대체하고 상기 내용의 나머지를 원상태로 유지하는 단계와; 상기 표시 제공의 유무에 따라 상기 내부 레지스터 수단의 상기 내용을 상기 선택적으로 정렬된 다중 바이트의 외부 메모리 위치에 조건부로 스토어하는 단계를 포함하는 것을 특징으로 하는 아토믹 바이트 기입수행방법.
  2. 제1항에 있어서, 상기 조건부로 스토어하는 단계가 기억부를 실행하는 유무에 따라 상기 프로세서에 표시를 제공하는 단계를 추가로 포함하는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, 상기 표시를 로드하고 제공하는 단계는 하나의 명령에 의해 수행되는 것을 특징으로 하는 방법.
  4. 제2항에 있어서, 상기 표시를 조건부로 스토어하고 제공하는 단계는 하나의 명령에 의해 수행되는 것을 특징으로 하는 방법.
  5. 제1항에 있어서, 상기 표시제공단계는 상기 로드단계에 따라 세트되는 상태비트률 리세트 하는 것을 특징으로 하는 방법.
  6. 제5항에 있어서, 상기 상태 비트는 상기 프로세서에서 인터럽트나 예외가 발생할때 리세트 되는 것을 특징으로 하는 방법.
  7. 제1항에 있어서, 상기 메모리는 콰트워드(8바이트)나 롱워드(4바이트)경계로 정렬된것을 특징으로 하는 방법.
  8. 프로세서에 의해 외부 메모리에 있는 선택적으로 비정열된 바이트 위치에 기입하는 방법에 있어서, 상기 비정렬된 바이트 위치를 포함하는 선택적으로 정렬된 외부 메모리위치를 내부 레지스터 수단에 로드한 다음 상기 선택적으로 정렬된 외부 메모리위치에 대한 임의의 다른 기억부를 검출하는 단계와; 상기 선택적으로 정렬된 외부 메모리위치에 임의의 다른 기억부가 구성되었는지의 여부의 표시를 제공하는 단계와; 상기 내부 레지스터수단에 수정된 내용을 제공하기 위해 선택된 바이트를 기입될 새로운 값으로 대체하는 단계와; 상기 표시제공의 유무에 따라 상기 내부 레지스터 수단으로 부터 상기 선택적으로 정렬된 외부 메모리 위치에 상기 수정된 내용을 조건부로 스토어하는 단계를 포함하는 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 상기 표시를 로드하고 제공하는 단계는 하나의 명령에 의해 수행되며, 상기 조건부로 스토어하는 단계는 다른 하나의 명령에 의해 수행되는 것을 특징으로 하는 방법.
  10. 제8항에 있어서, 상기 표시를 제공하는 단계는 프로세서로 상기 로드단계시 세트되는 상태 비트를 리세트하는 것을 특징으로 하는 방법.
  11. 제8항에 있어서, 상기 메모르는 콰드워드(8바이트)나 롱워드(4바이트)경계로 정렬되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910010878A 1990-06-29 1991-06-28 멀티프로세서 또는 파이프 라인식 프로세서 시스템에서 데이타의 보존을 확실히 하는 방법 KR0185988B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/547,618 US5193167A (en) 1990-06-29 1990-06-29 Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
US547,618 1990-06-29

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KR920001334A true KR920001334A (ko) 1992-01-30
KR0185988B1 KR0185988B1 (ko) 1999-05-15

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US (1) US5193167A (ko)
EP (1) EP0465321B1 (ko)
JP (1) JP3055980B2 (ko)
KR (1) KR0185988B1 (ko)
CA (1) CA2045934A1 (ko)
DE (1) DE69127242T2 (ko)
TW (2) TW239198B (ko)

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
CA2045735A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Computer performance by eliminating branches
JPH0831032B2 (ja) * 1990-08-29 1996-03-27 三菱電機株式会社 データ処理装置
TW197505B (ko) * 1991-03-07 1993-01-01 Digital Equipment Corp
GB9112754D0 (en) * 1991-06-13 1991-07-31 Int Computers Ltd Data processing apparatus
JP3105197B2 (ja) 1991-06-24 2000-10-30 株式会社日立製作所 除算回路及び除算方法
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
US5491811A (en) * 1992-04-20 1996-02-13 International Business Machines Corporation Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994011828A2 (en) * 1992-11-09 1994-05-26 Ast Research, Inc. Write buffer with full rank byte gathering
JP3304444B2 (ja) * 1992-11-30 2002-07-22 富士通株式会社 ベクトル処理装置
EP0601715A1 (en) * 1992-12-11 1994-06-15 National Semiconductor Corporation Bus of CPU core optimized for accessing on-chip memory devices
US5568415A (en) * 1993-02-19 1996-10-22 Digital Equipment Corporation Content addressable memory having a pair of memory cells storing don't care states for address translation
US5406504A (en) * 1993-06-30 1995-04-11 Digital Equipment Multiprocessor cache examiner and coherency checker
US5555392A (en) * 1993-10-01 1996-09-10 Intel Corporation Method and apparatus for a line based non-blocking data cache
US5689695A (en) * 1993-11-30 1997-11-18 Texas Instruments Incorporated Conditional processor operation based upon result of two consecutive prior processor operations
US5802341A (en) * 1993-12-13 1998-09-01 Cray Research, Inc. Method for the dynamic allocation of page sizes in virtual memory
US5636374A (en) * 1994-01-04 1997-06-03 Intel Corporation Method and apparatus for performing operations based upon the addresses of microinstructions
TW260765B (ko) * 1994-03-31 1995-10-21 Ibm
JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
US5931945A (en) * 1994-04-29 1999-08-03 Sun Microsystems, Inc. Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits
JPH07334416A (ja) * 1994-06-06 1995-12-22 Internatl Business Mach Corp <Ibm> コンピュータ・システムにおけるページ・モード・メモリの初期設定の方法および手段
EP0702306A1 (en) * 1994-09-19 1996-03-20 International Business Machines Corporation System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter
JP3452989B2 (ja) * 1994-09-26 2003-10-06 三菱電機株式会社 中央処理装置
US6073211A (en) * 1994-12-13 2000-06-06 International Business Machines Corporation Method and system for memory updates within a multiprocessor data processing system
US5611073A (en) * 1995-02-09 1997-03-11 Delco Electronics Corp. Method of ensuring parameter coherency in a multi-processor system
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5704053A (en) * 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5815421A (en) * 1995-12-18 1998-09-29 Intel Corporation Method for transposing a two-dimensional array
US5778208A (en) * 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
US5907842A (en) * 1995-12-20 1999-05-25 Intel Corporation Method of sorting numbers to obtain maxima/minima values with ordering
US5751946A (en) * 1996-01-18 1998-05-12 International Business Machines Corporation Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor
US5958042A (en) * 1996-06-11 1999-09-28 Sun Microsystems, Inc. Grouping logic circuit in a pipelined superscalar processor
US6173366B1 (en) 1996-12-02 2001-01-09 Compaq Computer Corp. Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage
US5893145A (en) * 1996-12-02 1999-04-06 Compaq Computer Corp. System and method for routing operands within partitions of a source register to partitions within a destination register
US6061521A (en) * 1996-12-02 2000-05-09 Compaq Computer Corp. Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle
US5941938A (en) * 1996-12-02 1999-08-24 Compaq Computer Corp. System and method for performing an accumulate operation on one or more operands within a partitioned register
US5909572A (en) * 1996-12-02 1999-06-01 Compaq Computer Corp. System and method for conditionally moving an operand from a source register to a destination register
US6009505A (en) * 1996-12-02 1999-12-28 Compaq Computer Corp. System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot
US6052753A (en) * 1997-01-21 2000-04-18 Alliedsignal Inc. Fault tolerant data bus
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US20030069403A1 (en) * 1997-06-16 2003-04-10 Genentech, Inc. Secreted and transmembrane polypeptides and nucleic acids encoding the same
US6061765A (en) * 1997-10-24 2000-05-09 Compaq Computer Corporation Independent victim data buffer and probe buffer release control utilzing control flag
US6055605A (en) * 1997-10-24 2000-04-25 Compaq Computer Corporation Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
US6088771A (en) * 1997-10-24 2000-07-11 Digital Equipment Corporation Mechanism for reducing latency of memory barrier operations on a multiprocessor system
US6141734A (en) * 1998-02-03 2000-10-31 Compaq Computer Corporation Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
US6173414B1 (en) 1998-05-12 2001-01-09 Mcdonnell Douglas Corporation Systems and methods for reduced error detection latency using encoded data
US7206877B1 (en) 1998-12-22 2007-04-17 Honeywell International Inc. Fault tolerant data communication network
US6629209B1 (en) 1999-11-09 2003-09-30 International Business Machines Corporation Cache coherency protocol permitting sharing of a locked data granule
US6629212B1 (en) 1999-11-09 2003-09-30 International Business Machines Corporation High speed lock acquisition mechanism with time parameterized cache coherency states
US6625701B1 (en) 1999-11-09 2003-09-23 International Business Machines Corporation Extended cache coherency protocol with a modified store instruction lock release indicator
US6629214B1 (en) 1999-11-09 2003-09-30 International Business Machines Corporation Extended cache coherency protocol with a persistent “lock acquired” state
US6549989B1 (en) 1999-11-09 2003-04-15 International Business Machines Corporation Extended cache coherency protocol with a “lock released” state
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6678810B1 (en) * 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US6678820B1 (en) * 2000-03-30 2004-01-13 International Business Machines Corporation Processor and method for separately predicting conditional branches dependent on lock acquisition
US6766442B1 (en) 2000-03-30 2004-07-20 International Business Machines Corporation Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
US6658558B1 (en) 2000-03-30 2003-12-02 International Business Machines Corporation Branch prediction circuit selector with instruction context related condition type determining
US6973561B1 (en) * 2000-12-04 2005-12-06 Lsi Logic Corporation Processor pipeline stall based on data register status
US7472259B2 (en) * 2000-12-06 2008-12-30 Analog Devices, Inc. Multi-cycle instructions
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
US6877085B2 (en) 2001-11-30 2005-04-05 Broadcom Corporation Mechanism for processing speclative LL and SC instructions in a pipelined processor
US6892260B2 (en) * 2001-11-30 2005-05-10 Freescale Semiconductor, Inc. Interrupt processing in a data processing system
US7099974B2 (en) * 2003-03-20 2006-08-29 International Business Machines Corporation Method, apparatus, and system for reducing resource contention in multiprocessor systems
US7254698B2 (en) * 2003-05-12 2007-08-07 International Business Machines Corporation Multifunction hexadecimal instructions
US7437541B2 (en) * 2004-07-08 2008-10-14 International Business Machiens Corporation Atomically updating 64 bit fields in the 32 bit AIX kernel
US7243210B2 (en) * 2005-05-31 2007-07-10 Atmel Corporation Extracted-index addressing of byte-addressable memories
US7680989B2 (en) * 2005-08-17 2010-03-16 Sun Microsystems, Inc. Instruction set architecture employing conditional multistore synchronization
US7480771B2 (en) 2005-08-17 2009-01-20 Sun Microsystems, Inc. Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US8078846B2 (en) * 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US8078843B2 (en) 2008-01-31 2011-12-13 International Business Machines Corporation Facilitating processing in a computing environment using an extended drain instruction
US9003170B2 (en) * 2009-12-22 2015-04-07 Intel Corporation Bit range isolation instructions, methods, and apparatus
US8799583B2 (en) 2010-05-25 2014-08-05 International Business Machines Corporation Atomic execution over accesses to multiple memory locations in a multiprocessor system
CN102402485B (zh) * 2010-09-16 2014-05-28 安凯(广州)微电子技术有限公司 Nandflash参数探测方法
US9164771B2 (en) * 2012-06-29 2015-10-20 Avaya Inc. Method for thread reduction in a multi-thread packet processor
US10114752B2 (en) 2014-06-27 2018-10-30 International Business Machines Corporation Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
US20150378904A1 (en) * 2014-06-27 2015-12-31 International Business Machines Corporation Allocating read blocks to a thread in a transaction using user specified logical addresses
CN106201440B (zh) * 2016-06-28 2018-10-23 上海兆芯集成电路有限公司 字符串比较指令优化的中央处理单元以及其操作方法
GB2563384B (en) * 2017-06-07 2019-12-25 Advanced Risc Mach Ltd Programmable instruction buffering
US10725937B2 (en) * 2018-07-30 2020-07-28 International Business Machines Corporation Synchronized access to shared memory by extending protection for a store target address of a store-conditional request
US11068407B2 (en) 2018-10-26 2021-07-20 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
US10884740B2 (en) 2018-11-08 2021-01-05 International Business Machines Corporation Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US11163575B2 (en) * 2019-04-03 2021-11-02 Microsoft Technology Licensing, Llc Widening memory access to an aligned address for unaligned memory operations
US11106608B1 (en) 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
US11693776B2 (en) 2021-06-18 2023-07-04 International Business Machines Corporation Variable protection window extension for a target address of a store-conditional request

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231652A (ja) * 1983-06-13 1984-12-26 Hitachi Ltd メモリアクセス・オ−バラツプ検出方式
US4561051A (en) * 1984-02-10 1985-12-24 Prime Computer, Inc. Memory access method and apparatus in multiple processor systems
JPS6167156A (ja) * 1984-09-07 1986-04-07 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ読取り／変更装置
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
EP0363176B1 (en) * 1988-10-07 1996-02-14 International Business Machines Corporation Word organised data processors

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EP0465321A3 (en) 1994-07-06
CA2045934A1 (en) 1991-12-30
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EP0465321B1 (en) 1997-08-13
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US5193167A (en) 1993-03-09
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