KR910005459A - 반도체메모리장치 및 그 제조방법 - Google Patents

반도체메모리장치 및 그 제조방법 Download PDF

Info

Publication number
KR910005459A
KR910005459A KR1019900012363A KR900012363A KR910005459A KR 910005459 A KR910005459 A KR 910005459A KR 1019900012363 A KR1019900012363 A KR 1019900012363A KR 900012363 A KR900012363 A KR 900012363A KR 910005459 A KR910005459 A KR 910005459A
Authority
KR
South Korea
Prior art keywords
transistor
memory device
fuse
memory cell
cell array
Prior art date
Application number
KR1019900012363A
Other languages
English (en)
Other versions
KR930010730B1 (ko
Inventor
가즈히코 노보리
마고토 다키자와
시게후미 이시구로
사토시 니카와
다이라 이와세
마사니치 아사노
가즈오 요네하라
고지 사이토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910005459A publication Critical patent/KR910005459A/ko
Application granted granted Critical
Publication of KR930010730B1 publication Critical patent/KR930010730B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)

Abstract

내용 없음

Description

반도체메모리장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일 실시예에 의한 반도체메모리장치가 갖추고 있는 용장회로에서, 기록워드선의 전위, 휴즈에 흐르는 프로그램전류, 접지배선의 전위변화를 나타낸 설명도
제2도는 동 용장회로로서 적용이 가능한 회로의 구성을 나타낸 회로도.

Claims (2)

  1. 정규메모리셀 어레이와 예비메모리셀 어레이를 갖춘 용장 회로쪽의 반도체메모리장치에 있어서, 상기 예비메모리셀 어레이를 구성할 각 예비메모리셀(C1,C2)은 드레인이 독출용 데이터선(BL1,BL2)에 접속되고 소스가 휴즈(F1,F2)를 매개해서 전원에 접속되며 워드선독출용(WL)에 의해서 선택되는 제1트랜지스터(T3,T4)와, 상기 제1트랜지스터와 휴즈의 접속점 및 어스간에 접속된 제2트랜지스터(T1,T2)를 갖추고,상기 제2트랜지스터(T1,T2)를 기록선(L1,L2)으로 선택함으로써 상기 휴즈에 용단전류를 흘러서 상기 휴즈를 선택적으로 용단해서 상기 독출용 데이터선의 방전류로를 차단가능하게 한 반도체메모리장치에 있어서, 상기 예비메모리셀(C1,C2)의 어느 것에 상기 제2트랜지스터(T1,T2)가 상기 기록선의 선택에 의해 도통되어 상기 휴즈에 용단전류가 흘렀을때에, 다른 예비메모리셀에 접속된 기록선에 발생하는 대 어스 전위차(VGS)보다도 높은 문턱값전압(Vth)을 상기 제2트랜지스터가 갖추는 것을 특징으로 하는 반도체메모리장치.
  2. 정규메모리셀 어레이와 예비메모리셀 어레이를 갖춘 용장회로쪽의 반도체메모리장치에 있어서, 상기 예비메모리셀 어레이를 구성하는 각 예비메모리셀(C1,C2)은 드레인이 독출용 데이터선에 접속되고 소스가 휴즈(F1,F2)를 매개해서 전원에 접속되며 독출용 워드선(WL)에 의해서 선택되는 제1트랜지스터(T3,T4)와, 상기 제1트랜지스터와 휴즈의 접속점 및 어스간에 접속된 제2트랜지스터(T1,T2)를 갖추고, 상기 제2트랜지스터를 기록선(L1,L2)으로 선택함으로써 상기 휴즈에 용단전류를 흘러서 상기 휴즈를 선택적으로 용단하여 상기 독출용 데이터선의 방전류로를 차단가능하게 한 반도체메모리장치의 제조방법에 있어서, 반도체기판(1) 표면의 상기 제2트랜지스터(T1,T2)형성영역의 채널부분 및 이 제2트랜지스터와 동일한 도전형의 다른 트랜지스터의 채널부분에 불순물이온(B+)을 주입하는 공정과, 상기 제2트랜지스터(T1,T2)의 채널부분 및 이 제2트랜지스터와 역도전형의 트랜지스터의 채널부분에 상기 불순물이온(B+)을 주입하는 공정을 구비함으로써 상기 제2트랜지스터(T1,T2)의
    채널부분에 상기 불순물이온을 거듭 주입하는 것을 특징으로 하는 반도체메모리장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900012363A 1989-08-11 1990-08-11 반도체메모리장치 및 그 제조방법 KR930010730B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1-209169 1989-08-11
JP20916989 1989-08-11
JP2091104A JP2509730B2 (ja) 1989-08-11 1990-04-05 半導体メモリ装置及びその製造方法
JP2-091104 1990-04-05

Publications (2)

Publication Number Publication Date
KR910005459A true KR910005459A (ko) 1991-03-30
KR930010730B1 KR930010730B1 (ko) 1993-11-08

Family

ID=26432578

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900012363A KR930010730B1 (ko) 1989-08-11 1990-08-11 반도체메모리장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5257230A (ko)
EP (1) EP0417484B1 (ko)
JP (1) JP2509730B2 (ko)
KR (1) KR930010730B1 (ko)
DE (1) DE69020461T2 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2981346B2 (ja) * 1992-08-31 1999-11-22 シャープ株式会社 読み出し専用半導体記憶装置
US5677888A (en) * 1995-06-06 1997-10-14 Integrated Device Technology, Inc. Redundancy circuit for programmable integrated circuits
JP3230795B2 (ja) * 1995-09-29 2001-11-19 シャープ株式会社 読み出し専用半導体記憶装置
US6031771A (en) * 1996-10-28 2000-02-29 Macronix International Co., Ltd. Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements
US5889711A (en) * 1997-10-27 1999-03-30 Macronix International Co., Ltd. Memory redundancy for high density memory
US5896327A (en) * 1997-10-27 1999-04-20 Macronix International Co., Ltd. Memory redundancy circuit for high density memory with extra row and column for failed address storage
JP4639030B2 (ja) * 2002-11-18 2011-02-23 パナソニック株式会社 半導体記憶装置
US7583554B2 (en) 2007-03-02 2009-09-01 Freescale Semiconductor, Inc. Integrated circuit fuse array
US8542549B2 (en) 2011-08-08 2013-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse bit cell
US8760955B2 (en) * 2011-10-21 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse memory arrays
US8610243B2 (en) 2011-12-09 2013-12-17 Globalfoundries Inc. Metal e-fuse with intermetallic compound programming mechanism and methods of making same
US20140268983A1 (en) * 2013-03-15 2014-09-18 GlobalFoundries, Inc. Otprom array with leakage current cancelation for enhanced efuse sensing
GB2571641B (en) 2015-09-01 2020-02-19 Lattice Semiconductor Corp Multi-time programmable non-volatile memory cell
KR102389817B1 (ko) * 2016-01-28 2022-04-22 삼성전자주식회사 디스차아지 회로를 갖는 퓨즈 메모리
US11088140B2 (en) 2019-08-27 2021-08-10 Nanya Technology Corporation Multiple semiconductor elements with different threshold voltages
US11177010B1 (en) * 2020-07-13 2021-11-16 Qualcomm Incorporated Bitcell for data redundancy

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4230504B1 (en) * 1978-04-27 1997-03-04 Texas Instruments Inc Method of making implant programmable N-channel rom
JPS5843838B2 (ja) * 1979-02-28 1983-09-29 富士通株式会社 読取り専用メモリ
JPS584969A (ja) * 1981-06-30 1983-01-12 Fujitsu Ltd 半導体装置
JPS60201598A (ja) * 1984-03-23 1985-10-12 Fujitsu Ltd 半導体集積回路
US4654830A (en) * 1984-11-27 1987-03-31 Monolithic Memories, Inc. Method and structure for disabling and replacing defective memory in a PROM
JPH0235699A (ja) * 1988-07-26 1990-02-06 Nec Corp 化合物半導体メモリデバイス
JPH0817039B2 (ja) * 1988-08-19 1996-02-21 株式会社東芝 半導体メモリセル

Also Published As

Publication number Publication date
EP0417484B1 (en) 1995-06-28
EP0417484A3 (en) 1992-01-02
DE69020461D1 (de) 1995-08-03
DE69020461T2 (de) 1996-01-11
JP2509730B2 (ja) 1996-06-26
KR930010730B1 (ko) 1993-11-08
US5257230A (en) 1993-10-26
JPH03155652A (ja) 1991-07-03
EP0417484A2 (en) 1991-03-20

Similar Documents

Publication Publication Date Title
US6521958B1 (en) MOSFET technology for programmable address decode and correction
US4404659A (en) Programmable read only memory
US4639895A (en) Semiconductor memory device
EP0525680B1 (en) Data latch circuit having non-volatile memory cell
KR910005459A (ko) 반도체메모리장치 및 그 제조방법
US4964084A (en) Static random access memory device with voltage control circuit
US4207615A (en) Non-volatile ram cell
KR960019315A (ko) 불휘발성 반도체 메모리장치
KR900003895A (ko) 반도체메모리셀 및 반도체메모리장치
US5748531A (en) Common source line control circuit for preventing snap back breakdown
JPS61501356A (ja) 不揮発性ラッチ
US5572464A (en) Semiconductor memory device and method of using the same
KR900000586B1 (ko) 리드 온리 메모리(Read Only Memory)회로
KR100346991B1 (ko) 반도체 기억 장치
US4590388A (en) CMOS spare decoder circuit
KR930004710B1 (ko) 반도체 메모리
US6018475A (en) MOS memory point
EP0100339A1 (en) A circuit for applying a high voltage signal to a fusible link
KR910006997A (ko) 기생용량에 의해 야기된 오동작을 방지하기 위한 eprom의 디코더 회로
EP0015676B1 (en) A read only memory
US8630108B2 (en) MOSFET fuse and array element
US4661926A (en) Bit line gain circuit for read only memory
EP0206576A2 (en) Improvements in semiconductor memories
JPH08316427A (ja) 半導体集積回路装置
KR100567356B1 (ko) 이중 셀 전원 전압을 가지는 에스램

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091028

Year of fee payment: 17

EXPY Expiration of term