KR900002621B1 - 래치엎 현상을 감소시키는 상보형 반도체장치 - Google Patents

래치엎 현상을 감소시키는 상보형 반도체장치 Download PDF

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Publication number
KR900002621B1
KR900002621B1 KR1019860006673A KR860006673A KR900002621B1 KR 900002621 B1 KR900002621 B1 KR 900002621B1 KR 1019860006673 A KR1019860006673 A KR 1019860006673A KR 860006673 A KR860006673 A KR 860006673A KR 900002621 B1 KR900002621 B1 KR 900002621B1
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KR
South Korea
Prior art keywords
circuit
potential
substrate
transistor
gate
Prior art date
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Expired
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KR1019860006673A
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English (en)
Korean (ko)
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KR870002653A (ko
Inventor
또미오 나까노
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
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Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Publication of KR870002653A publication Critical patent/KR870002653A/ko
Application granted granted Critical
Publication of KR900002621B1 publication Critical patent/KR900002621B1/ko
Expired legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Power Engineering (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1019860006673A 1985-08-14 1986-08-13 래치엎 현상을 감소시키는 상보형 반도체장치 Expired KR900002621B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP178958 1985-08-14
JP60-178958 1985-08-14
JP60178958A JPS6238591A (ja) 1985-08-14 1985-08-14 相補型の半導体メモリ装置

Publications (2)

Publication Number Publication Date
KR870002653A KR870002653A (ko) 1987-04-06
KR900002621B1 true KR900002621B1 (ko) 1990-04-20

Family

ID=16057632

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860006673A Expired KR900002621B1 (ko) 1985-08-14 1986-08-13 래치엎 현상을 감소시키는 상보형 반도체장치

Country Status (5)

Country Link
US (1) US4862415A (https=)
EP (1) EP0222472B1 (https=)
JP (1) JPS6238591A (https=)
KR (1) KR900002621B1 (https=)
DE (1) DE3685871T2 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666443B2 (ja) * 1988-07-07 1994-08-24 株式会社東芝 半導体メモリセルおよび半導体メモリ
US4965466A (en) * 1989-07-19 1990-10-23 Motorola, Inc. Substrate injection clamp
DE69119439T2 (de) * 1990-02-05 1996-09-26 Texas Instruments Inc Substratvorspannung Detektorschaltung
EP0444602B1 (en) * 1990-02-26 1996-05-15 Nec Corporation Decoder circuit
JP3107556B2 (ja) * 1990-06-01 2000-11-13 株式会社東芝 ダイナミック型半導体記憶装置
US5341035A (en) * 1990-06-04 1994-08-23 Matsushita Electric Industrial Co., Ltd. Substrate potential generator
US5345422A (en) * 1990-07-31 1994-09-06 Texas Instruments Incorporated Power up detection circuit
KR0137857B1 (ko) * 1992-06-02 1998-06-01 사또오 후미오 반도체 장치
JPH10502181A (ja) * 1994-06-20 1998-02-24 ネオマジック・コーポレイション メモリインタフェースのないグラフィックスコントローラ集積回路
KR0172333B1 (ko) * 1995-01-16 1999-03-30 김광호 반도체 메모리 장치의 전원 승압 회로
JPH08272467A (ja) * 1995-03-31 1996-10-18 Mitsubishi Electric Corp 基板電位発生回路
FR2735922B1 (fr) * 1995-06-21 1997-08-22 Sgs Thomson Microelectronics Circuit generateur de tension negative du type pompe de charge
JPH1079193A (ja) * 1996-07-11 1998-03-24 Toshiba Microelectron Corp 半導体装置
US5883544A (en) * 1996-12-03 1999-03-16 Stmicroelectronics, Inc. Integrated circuit actively biasing the threshold voltage of transistors and related methods
US6657241B1 (en) 1998-04-10 2003-12-02 Cypress Semiconductor Corp. ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices
US6292391B1 (en) 2000-03-28 2001-09-18 Silicon Storage Technology, Inc. Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM
EP1965425A1 (en) * 2007-03-01 2008-09-03 Infineon Technologies Austria AG Reverse voltage protected integrated circuit arrangement
US8013475B2 (en) 2007-03-15 2011-09-06 Infineon Technologies Ag Reverse voltage protected integrated circuit arrangement for multiple supply lines
JP6263833B2 (ja) * 2012-10-22 2018-01-24 株式会社ソシオネクスト 電子回路および半導体装置
FR3018944A1 (fr) * 2014-03-21 2015-09-25 St Microelectronics Rousset Dispositif de memoire associant un plan memoire du type sram et un plan-memoire du type non volatil, durci contre des basculements accidentels
US10204906B2 (en) * 2016-12-16 2019-02-12 Intel Corporation Memory with single-event latchup prevention circuitry

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951071B2 (ja) * 1976-02-09 1984-12-12 日本電気株式会社 メモリ保護回路
US4337524A (en) * 1980-02-07 1982-06-29 Mostek Corporation Backup power circuit for biasing bit lines of a static semiconductor memory
US4322675A (en) * 1980-11-03 1982-03-30 Fairchild Camera & Instrument Corp. Regulated MOS substrate bias voltage generator for a static random access memory
US4638464A (en) * 1983-11-14 1987-01-20 International Business Machines Corp. Charge pump system for non-volatile ram
US4631421A (en) * 1984-08-14 1986-12-23 Texas Instruments CMOS substrate bias generator
US4678941A (en) * 1985-04-25 1987-07-07 International Business Machines Corporation Boost word-line clock and decoder-driver circuits in semiconductor memories

Also Published As

Publication number Publication date
US4862415A (en) 1989-08-29
JPH0468715B2 (https=) 1992-11-04
DE3685871T2 (de) 1992-12-17
KR870002653A (ko) 1987-04-06
EP0222472B1 (en) 1992-07-01
JPS6238591A (ja) 1987-02-19
DE3685871D1 (de) 1992-08-06
EP0222472A2 (en) 1987-05-20
EP0222472A3 (en) 1989-11-29

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