KR900002425A - Highly Concentrated Source Region and Formation Method of Semiconductor Devices Using Selective Sidewall Doping Technique (SSWDT) - Google Patents

Highly Concentrated Source Region and Formation Method of Semiconductor Devices Using Selective Sidewall Doping Technique (SSWDT) Download PDF

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Publication number
KR900002425A
KR900002425A KR1019880009187A KR880009187A KR900002425A KR 900002425 A KR900002425 A KR 900002425A KR 1019880009187 A KR1019880009187 A KR 1019880009187A KR 880009187 A KR880009187 A KR 880009187A KR 900002425 A KR900002425 A KR 900002425A
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South Korea
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layer
etching
mask pattern
source region
forming
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KR1019880009187A
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Korean (ko)
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KR910006748B1 (en
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오상묵
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정몽헌
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

내용 없음No content

Description

선택적 측면벽 도핑기술(SSWDT)을 이용한 반도체 소자의 고농도 소스영역 형성방법A method for forming a high concentration source region of a semiconductor device using selective sidewall doping technique (SSWDT)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제2c도는 본 발명의 소스영역 형성방법을 설명하기 위한 도시도로서, 제1a도는 본 발명을 설명하기 위해 N+기판에 에피텍셜 성장층을 형성시키고 그 위에 마스크층을 형성한 후 포토 레지스터층을 코팅한 상태의 단면도.1A to 2C are diagrams for explaining a method of forming a source region of the present invention. FIG. 1A is a diagram illustrating an epitaxial growth layer formed on an N + substrate and a mask layer formed thereon to illustrate the present invention. Cross section of the photoresist layer coated.

제1b도는 제1a도에서 포토 레지스터층의 일부분을 제거한 상태의 단면도.FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG.

제1c도는 제1b도에서 마스크 패턴을 형성한 다음 포토레지스터층을 제거한 상태의 단면도.FIG. 1C is a cross-sectional view of a state in which a photoresist layer is removed after forming a mask pattern in FIG. 1B.

제2a도는 제1c도의 공정후에 에피텍셜 성장층을 소정깊이로 에칭한후 도프 산화물을 침착한 상태의 단면도.FIG. 2A is a cross-sectional view of a state in which dope oxide is deposited after the epitaxial growth layer is etched to a predetermined depth after the process of FIG. 1C. FIG.

제2b도는 제2a도 공정후 산화막 스페이서 에칭(SPACER ETCHING)으로 스페이서를 형성하여 도핑한 상태의 단면도.FIG. 2B is a cross-sectional view of the spacer layer formed by doping oxide spacer etching after the process of FIG.

제2c도는 제2b도 상태에서 트렌치 에칭을 행하여 측면벽에 선택으로 도핑된 소스영역이 형성되고 도프산화물을 제거한 상태의 단면도.FIG. 2C is a cross-sectional view of a state in which a doped source region is selectively formed on a side wall by performing trench etching in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : N+(또는 P+)기판 2 : 산화물(OXIDE)1: N + (or P + ) substrate 2: Oxide

3 : 질화물(NITRIDE) 4 : 포토 레지스터층(PHOTO RESISTER LAYER)3: NITRIDE 4: Photo Register Layer (PHOTO RESISTER LAYER)

5 : 도프산화물 6 : 도핑영역(소스영역)5: doped oxide 6: doped region (source region)

7 : 에피텍셜 성장층7: epitaxial growth layer

Claims (1)

메가 D RAM급 이상의 반도체 고집적 소자의 소스영역 형성방법에 있어서, N+(혹은 P+)기판에 에피텍셜 성장층상에 산화물층을 침착하고 그위에 질화물층을 도핑하여 마스크층을 형성한 다음, 포토 레지스터층을 코팅하는 공정과, 상기 포토레지스터층의 일부를 제거시켜 노출된 상기 성장층 표면까지 에칭하여 마스크 패턴을 형성한후, 포토레지스터층을 완전히 제거하는 공정과, 마스크 패턴 형성 공정후에 노출된 에피텍셜 성장층 부위를 에칭처리하는 공정과, 상기 마스크 패턴 및 성장층의 에칭홈상에 BSG 또는 PSG 물질을 일정한 두께로 침착한후 산화막 스페이서 에칭을 행하여 선택적으로 도프산화물을 적당하게 남겨서 열처리하여 에피텍셜 성장층 내부에 상기 물질이 주입되는 도핑영역을 형성하고, 상기 침착물질을 에칭처리로 제거하는 공정과, 상기 도핑영역의 좌우측면을 남기고 실리콘 웨이퍼에 실제 마스크 패턴 폭보다 작은 폭을 갖는 트렌치 구조를 형성하는 공정으로 이루어지는 것을 특징으로 하는 선택적 측면벽 도핑기술을 이용한 소스영역 형성방법.In the method for forming a source region of a semiconductor DIC having a mega D RAM or higher, a oxide layer is deposited on an epitaxial growth layer on an N + (or P + ) substrate, and a doped nitride layer is formed thereon to form a mask layer. Coating a resist layer, removing a portion of the photoresist layer, etching to an exposed surface of the growth layer to form a mask pattern, completely removing the photoresist layer, and exposing the mask pattern after the mask pattern forming process. Etching the epitaxial growth layer, and depositing a BSG or PSG material on the mask pattern and the etching groove of the growth layer to a certain thickness, and then etching the oxide spacer to selectively heat the dope oxide with an appropriate amount of dope oxide. Forming a doped region to inject the material into the growth layer and removing the deposited material by etching; , The source region forming method using selective doping techniques, characterized in that the side wall, leaving the left and right sides of the doped region made of a step of forming a trench structure having a width smaller than the actual width of the mask pattern on silicon wafer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009187A 1988-07-22 1988-07-22 Semiconductor device source region forming method KR910006748B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880009187A KR910006748B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region forming method

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Application Number Priority Date Filing Date Title
KR1019880009187A KR910006748B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region forming method

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KR900002425A true KR900002425A (en) 1990-02-28
KR910006748B1 KR910006748B1 (en) 1991-09-02

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