KR940002974A - Single layer resist pattern formation method with improved etching selectivity - Google Patents

Single layer resist pattern formation method with improved etching selectivity Download PDF

Info

Publication number
KR940002974A
KR940002974A KR1019920013121A KR920013121A KR940002974A KR 940002974 A KR940002974 A KR 940002974A KR 1019920013121 A KR1019920013121 A KR 1019920013121A KR 920013121 A KR920013121 A KR 920013121A KR 940002974 A KR940002974 A KR 940002974A
Authority
KR
South Korea
Prior art keywords
single layer
resist pattern
layer resist
etching selectivity
polysilicon
Prior art date
Application number
KR1019920013121A
Other languages
Korean (ko)
Other versions
KR950009293B1 (en
Inventor
문승찬
김명선
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019920013121A priority Critical patent/KR950009293B1/en
Publication of KR940002974A publication Critical patent/KR940002974A/en
Application granted granted Critical
Publication of KR950009293B1 publication Critical patent/KR950009293B1/en

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 식각선택비가 향상된 단층레지스트 패턴(Single Layer Resist Pattern)형성방법에 관한 것으로, 식각할 폴리실리콘층위에 레지스트를 도포한후, 노광 및 현상공정으로 레지스트 패턴을 형성시킨 다음, 실리레이션(Silylaton) 공정 및 O2플라즈마 주입공정으로 레지스트 패턴의 표면을 SiO2화시키므로써 식각할 폴리실리콘층에 대한 레지스트 패턴의 식각선택비를 향상시큰 단층레지스트 패턴 형성방법을 기술한 것이다.The present invention relates to a method of forming a single layer resist pattern having improved etching selectivity, and after applying a resist on a polysilicon layer to be etched, forming a resist pattern by an exposure and developing process, It is described a method of forming a single layer resist pattern to improve the etching selectivity of the resist pattern to the polysilicon layer to be etched by SiO 2 process and the surface of the resist pattern by O 2 plasma injection process.

Description

식각선택비가 향상된 단층레지스트 패턴 형성방법Single layer resist pattern formation method with improved etching selectivity

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제4도는 본 발명의 식각선택비를 향상시킨 단층레지스트 패턴 형성단계를 나타낸 단면도.1 to 4 are cross-sectional views showing a step of forming a single layer resist pattern to improve the etching selectivity of the present invention.

제5도는 식각선택비가 향상된 단층레지스트 패턴을 이용하여 폴리실리콘 패턴을 형성한 상태의 단면도.5 is a cross-sectional view of a polysilicon pattern formed using a single layer resist pattern with improved etching selectivity.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 폴리실리콘층1 silicon substrate 2 polysilicon layer

2' : 폴리실리콘 패턴 3 : 단층레지스트(SLR)2 ': polysilicon pattern 3: single layer resist (SLR)

3' : 단층레지스트 패턴 4 : 마스크3 ': single layer resist pattern 4: mask

5 : 실리콘 확산영역 6 : 산화막5 silicon diffusion region 6 oxide film

Claims (1)

실리콘 기판상에 폴리실리콘층을 형성한 다음, 단층레지스트를 상기 폴리실리콘층상에 전반적으로 도포하는 단계와, 상기 단층레지스트상에 패턴이 형성된 마스크를 위치시킨 다음, 노광공정으로 단층레지스트의 예정부분을 광에 노출시킨 후, 현상공정을 실시하여 단층레지스트 패턴을 형성하는 단계로 이루어지는 단층레지스트 패턴 형성방법에 있어서, 상기 폴리실리콘층을 예정된 패턴으로 형성할 때에 식각마스크로 사용되는 단층레지스트와 식각되는 폴리실리콘층과의 식각선택비를 향상시키기 위하여, 상기 폴리실리콘층상에 형성된 단층레지스트 패턴 상부 표면에 실리레이션 공정으로 실리콘을 확산시켜 일정깊이의 실리콘 확산 영역을 형성하는 단계와, 상기 단층레지스트 패턴 상부표면의 실리를 확산영역에 RIE 식각장비나 플라즈마 식각장비로 O2플라즈마를 주입하여 상기 폴리실리콘층에 대하여 식각선택비가 높은 산화막을 형성하는 단계로 이루어지는 것을 특징으로 하는 식각선택비가 향상된 단층레지스트 패턴 형성방법.After the polysilicon layer is formed on the silicon substrate, a single layer resist is generally applied on the polysilicon layer, a patterned mask is placed on the single layer resist, and then a predetermined portion of the single layer resist is removed by an exposure process. A method of forming a single layer resist pattern comprising exposing to light and then developing a single layer resist pattern, wherein the polysilicon is etched with a single layer resist used as an etching mask when the polysilicon layer is formed in a predetermined pattern. In order to improve the etching selectivity with the silicon layer, the silicon diffusion region of a predetermined depth is formed by diffusing silicon on the upper surface of the single layer resist pattern formed on the polysilicon layer by a silicide process, and the upper surface of the single layer resist pattern RIE etching equipment or plasma And forming an oxide film having a high etching selectivity with respect to the polysilicon layer by injecting O 2 plasma into each device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920013121A 1992-07-23 1992-07-23 Single layer resist patterning method enhanced etching selective ration KR950009293B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920013121A KR950009293B1 (en) 1992-07-23 1992-07-23 Single layer resist patterning method enhanced etching selective ration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920013121A KR950009293B1 (en) 1992-07-23 1992-07-23 Single layer resist patterning method enhanced etching selective ration

Publications (2)

Publication Number Publication Date
KR940002974A true KR940002974A (en) 1994-02-19
KR950009293B1 KR950009293B1 (en) 1995-08-18

Family

ID=19336812

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920013121A KR950009293B1 (en) 1992-07-23 1992-07-23 Single layer resist patterning method enhanced etching selective ration

Country Status (1)

Country Link
KR (1) KR950009293B1 (en)

Also Published As

Publication number Publication date
KR950009293B1 (en) 1995-08-18

Similar Documents

Publication Publication Date Title
KR960005864A (en) Fine pattern formation method
KR940002974A (en) Single layer resist pattern formation method with improved etching selectivity
KR940002957A (en) Photosensitive film pattern formation method
KR940002664A (en) Photosensitive film pattern formation method
KR950021075A (en) Method for forming contact hole in semiconductor device
KR940004747A (en) Resist Pattern Forming Method
KR940009769A (en) Method of forming photoresist fine pattern of semiconductor device
KR900002420A (en) Method of forming high concentration source region and capacitor surface region of semiconductor device using selective sidewall doping technique (SSWDT)
KR950021096A (en) Contact hole formation method of semiconductor device
KR940007610A (en) Method of forming double photoresist fine pattern using oxidation treatment
KR950015575A (en) Method of Forming Photosensitive Film Pattern
JPS55130140A (en) Fabricating method of semiconductor device
KR970018041A (en) Method of forming fine contact hole in semiconductor device
KR940009770A (en) Silicide layer / polysilicon layer etching method
KR940016671A (en) Method of forming resist pattern for silicide
KR940016470A (en) Method for forming contact hole with inclined surface
KR970054111A (en) Manufacturing method of semiconductor device
KR950001918A (en) Gate pattern forming method using nitride film
KR940015669A (en) Micro pattern formation method using organic arc layer
KR950025913A (en) Micro pattern formation method of semiconductor device
KR960026578A (en) Field oxide film formation method of semiconductor device
KR970016754A (en) Method of manufacturing mask for semiconductor device
KR940004725A (en) Contact hole formation method using step relief mask
KR960002501A (en) Pattern formation method of semiconductor device
KR970054082A (en) Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040719

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee