KR940004747A - Resist Pattern Forming Method - Google Patents

Resist Pattern Forming Method Download PDF

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Publication number
KR940004747A
KR940004747A KR1019920015518A KR920015518A KR940004747A KR 940004747 A KR940004747 A KR 940004747A KR 1019920015518 A KR1019920015518 A KR 1019920015518A KR 920015518 A KR920015518 A KR 920015518A KR 940004747 A KR940004747 A KR 940004747A
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South Korea
Prior art keywords
pattern
resist pattern
mask
positive
positive resist
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KR1019920015518A
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Korean (ko)
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KR100235936B1 (en
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복철규
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김주용
현대전자산업 주식회사
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Priority to KR1019920015518A priority Critical patent/KR100235936B1/en
Publication of KR940004747A publication Critical patent/KR940004747A/en
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Publication of KR100235936B1 publication Critical patent/KR100235936B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 노광에너지를 증가시킴에 따라 패턴의 크기를 작게하는 특성을 가진 클리어필드마스크와 포지티브레지스트를 사용하여 클리어필드 마스크에 설계된 패턴폭보다 작은 패턴으로 필라패턴을 형성시킨 다음, 전반적으로 네가포지티브를 도포하여 필라패턴의 상부가 노출되도록 에치백한 후, 포지티브와 네가티브레지스트의 광 노출시의 상반된 특성을 이용하여 필라패턴을 제거시키므로써 미세선폭을 갖는 레지스트 패턴을 형성한 기술이다.The present invention uses a clearfield mask and a positive resist to reduce the size of the pattern as the exposure energy is increased, thereby forming a pillar pattern in a pattern smaller than the pattern width designed in the clearfield mask, and then generally negative. After applying the etch back to expose the upper portion of the pillar pattern, by removing the pillar pattern by using the opposite characteristics of the positive and negative resist light exposure, a resist pattern having a fine line width is formed.

Description

레지스트 패턴형성방법Resist Pattern Forming Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도 내지 제2g도는 본 발명에 의한 클리어필드마스크와 포지티브 및 네가티브레지스트를 이용하여 레지스트 패턴을 형성하는 단계를 나타낸 반도체 소자의 단면도.2A to 2G are cross-sectional views of a semiconductor device showing a step of forming a resist pattern using a clear field mask and positive and negative resists according to the present invention.

Claims (4)

반도체 소자의 레지스트 패턴형성방법에 있어서, 실리콘 웨이퍼상에 콘택홀이 형성될 물질층을 형성한 후, 상기 물질층상에 포지티브레지스트를 도포하는 단계와, 상기 포지티브레지스트 상에 패턴이 형성된 클리어필드마스크를 위치 시킨 후, 노광공정을 실시 하는 단계와, 상기 노광공정에 의하여 광에 조사된 부분을 현상공정으로 제거시켜 포지티브레지스트 패턴을 형성하는 단계와, 상기 포지티브레지스트 패턴을 포함한 물질층 상부에 전반적으로 네가티브레지스트를 도포하는 단계와, 상기 도포된 네가티브레지스트를 현상액을 사용하여 상기 포지티브레지스트 패턴의 상부가 노출될때까지 에치백한 후, 마스크 없이 전면에 걸쳐 노광공정을 실시하는 단계와, 상기 네가티브레지스트 및 포지티브레지스트 패턴이 상기 전면노광공정에 의하여 광에 조사된 상태에서 현상공정을 실시하여 포지티브레지스트 패턴을 현상 제거하여 후공정의 콘택홀을 형성하기 위한 네가티브레지스트 패턴홀을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 레지스트 패턴형성방법.A method of forming a resist pattern of a semiconductor device, comprising: forming a material layer on which a contact hole is to be formed on a silicon wafer, and then applying a positive resist on the material layer, and forming a clear field mask on which the pattern is formed on the positive resist. After positioning, performing an exposure process, removing a portion irradiated with light by the exposure process by a developing process to form a positive resist pattern, and generally having an overall negative layer on the material layer including the positive resist pattern. Applying a resist, etching the applied negative resist using a developer until the top of the positive resist pattern is exposed, and then performing an exposure process over the entire surface without a mask; and the negative resist and the positive The resist pattern is formed by the front exposure process. And developing a negative resist pattern hole to form a negative resist pattern hole for forming a subsequent contact hole by developing and removing the positive resist pattern in a state irradiated with light. 제1항에 있어서, 상기 클리어필드 마스크를 이용한 노광공정과 상기 마스크 없이 전면 노광공정시 조사한 광은 동일한 파장을 갖는 광인 것을 특징으로 하는 반도체 소자의 레지스트 패턴형성방법The method of claim 1, wherein the light irradiated during the exposure process using the clear field mask and the entire surface exposure process without the mask are light having the same wavelength. 제1항에 있어서, 상기 포지티브레지스트 패턴의 패턴선폭은 패턴이 형성된 클리어필드 마스크의 마스크 패턴선폭보다 같거나 작게 형성되는 것을 특징으로 하는 반도체 소자의 레지스트 패턴형성방법.The method of claim 1, wherein the pattern line width of the positive resist pattern is equal to or smaller than the mask pattern line width of the clear field mask on which the pattern is formed. 제1항에 있어서, 상기 후공정의 콘택홀을 형성하기 위한 네가티브레지스트 패턴 홀의 선폭은 상기 포지티브레지스트 패턴의 선폭과 동일한 것을 특징으로 하는 반도체 소자의 레지스트 패턴형성 방법.The method of claim 1, wherein a line width of the negative resist pattern hole for forming the contact hole in the post process is the same as a line width of the positive resist pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920015518A 1992-08-28 1992-08-28 Method for manufacturing resist pattern KR100235936B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015518A KR100235936B1 (en) 1992-08-28 1992-08-28 Method for manufacturing resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015518A KR100235936B1 (en) 1992-08-28 1992-08-28 Method for manufacturing resist pattern

Publications (2)

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KR940004747A true KR940004747A (en) 1994-03-15
KR100235936B1 KR100235936B1 (en) 1999-12-15

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KR100235936B1 (en) 1999-12-15

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