KR940016501A - Method of forming micro contact hole by multi mask - Google Patents

Method of forming micro contact hole by multi mask Download PDF

Info

Publication number
KR940016501A
KR940016501A KR1019920027060A KR920027060A KR940016501A KR 940016501 A KR940016501 A KR 940016501A KR 1019920027060 A KR1019920027060 A KR 1019920027060A KR 920027060 A KR920027060 A KR 920027060A KR 940016501 A KR940016501 A KR 940016501A
Authority
KR
South Korea
Prior art keywords
contact hole
mask
photoresist film
micro contact
negative photoresist
Prior art date
Application number
KR1019920027060A
Other languages
Korean (ko)
Other versions
KR960006695B1 (en
Inventor
김진섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027060A priority Critical patent/KR960006695B1/en
Publication of KR940016501A publication Critical patent/KR940016501A/en
Application granted granted Critical
Publication of KR960006695B1 publication Critical patent/KR960006695B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

본 발명은 고집적 반도체 소자의 다중마스크에 의한 미세콘택홀 형성방법에 관한것으로, 광이 마스크를 통과할때 발생하는 회전 및 근접효과를 줄이기 위하여 패턴하고자 하는 하부층 상부에 네가티브 감광막을 도포한 다음, 예정된 콘택홀영역 상부와 겹쳐지는 가로방향의 크롬패턴을 갖는 제 1 마스크를 사용하여 네가티브 감광막을 노광시키는 단계와, 다시 예정된 콘택홀영역 상부와 겹쳐지는 세로방향의 크롬패턴을 갖는 제 2 마스크를 사용하여 네가티브 감광막을 노광시키는 단계와, 노광된 감광막을 제거하여 콘택홀용 감광막 패턴을 형성하는 단계로 이루어지는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a micro contact hole by using a multi-mask of a highly integrated semiconductor device. Exposing a negative photoresist film using a first mask having a horizontal chrome pattern overlapping the upper contact hole region, and again using a second mask having a vertical chrome pattern overlapping the predetermined upper contact hole region A negative photoresist film is exposed, and the exposed photoresist film is removed to form a contact hole photoresist pattern.

Description

다중마스크에 의한 미세콘택홀 형성방법Method of forming micro contact hole by multi mask

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명에 의해 콘택홀용 감광막패턴을 형성하는 단계를 도시한 단면도.2A to 2E are sectional views showing the step of forming a photoresist pattern for a contact hole according to the present invention.

Claims (1)

콘택홀용 감광막패턴 형성방법에 있어서, 패턴하고자 하는 하부층 상부에 네가티브 감광막을 도포한 다음, 예정된 콘택홀영역 상부와 겹쳐지는 가로방향의 크롬패턴을 갖는 제 1 마스크를 사용하여 네가티브 감광막을 노광시키는 단계와, 다시 예정된 콘택홀영역 상부와 겹쳐지는 세로방향의 크롬패턴을 갖는 제 2 마스크를 사용하여 네가티브 감광막을 노광시키는 단계와, 노광된 감광막을 제거하여 콘택홀용 감광막패턴을 형성하는 단계로 이루어지는 것을 특징으로 하는 다중마스크에 의한 미세콘택홀 형성방법.A method for forming a contact hole photoresist pattern, comprising: applying a negative photoresist film on an upper portion of a lower layer to be patterned, and then exposing the negative photoresist film by using a first mask having a horizontal chrome pattern overlapping an upper portion of a predetermined contact hole region; Exposing the negative photoresist film using a second mask having a vertical chrome pattern overlapping the upper portion of the predetermined contact hole region, and removing the exposed photoresist film to form a contact hole photoresist pattern. Method for forming a fine contact hole by using a multi-mask. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027060A 1992-12-31 1992-12-31 Fine contact hole forming method by multi-mask KR960006695B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027060A KR960006695B1 (en) 1992-12-31 1992-12-31 Fine contact hole forming method by multi-mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027060A KR960006695B1 (en) 1992-12-31 1992-12-31 Fine contact hole forming method by multi-mask

Publications (2)

Publication Number Publication Date
KR940016501A true KR940016501A (en) 1994-07-23
KR960006695B1 KR960006695B1 (en) 1996-05-22

Family

ID=19348208

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027060A KR960006695B1 (en) 1992-12-31 1992-12-31 Fine contact hole forming method by multi-mask

Country Status (1)

Country Link
KR (1) KR960006695B1 (en)

Also Published As

Publication number Publication date
KR960006695B1 (en) 1996-05-22

Similar Documents

Publication Publication Date Title
KR970018110A (en) Pattern Forming Method of Semiconductor Device
KR940016501A (en) Method of forming micro contact hole by multi mask
KR970008372A (en) Fine Pattern Formation Method of Semiconductor Device
KR950034748A (en) Photoresist pattern formation method
KR950015617A (en) Manufacturing method of fine pattern of semiconductor device
KR950019919A (en) Micro pattern formation method of semiconductor device
KR970008321A (en) Method of forming photoresist pattern of semiconductor device
KR940004747A (en) Resist Pattern Forming Method
KR970013064A (en) Micro pattern formation method of semiconductor device
KR920005352A (en) Micro pattern formation method using multilayer resist
KR930006839A (en) Micro Pattern Formation Method in Semiconductor Manufacturing Process
KR970049069A (en) Fine pattern exposure method of semiconductor device
KR970018028A (en) Metal contact formation method of semiconductor device
KR950025927A (en) Semiconductor device manufacturing method
KR900017174A (en) Method of forming fine pattern of semiconductor
KR960002592A (en) Manufacturing method of semiconductor device
KR970003561A (en) Fine pattern formation method
KR940015704A (en) Method of forming photoresist pattern for silicide
KR960032741A (en) Fine Pattern Formation Method of Semiconductor Device
KR970003559A (en) Method of forming fine pattern of semiconductor device
KR950004390A (en) Pattern formation method of semiconductor device
KR950021045A (en) Method of forming fine pattern of semiconductor device
KR940015669A (en) Micro pattern formation method using organic arc layer
KR940016689A (en) Metal wiring planarization method of semiconductor device
KR950025913A (en) Micro pattern formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090427

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee