KR970003561A - Fine pattern formation method - Google Patents

Fine pattern formation method Download PDF

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Publication number
KR970003561A
KR970003561A KR1019950019098A KR19950019098A KR970003561A KR 970003561 A KR970003561 A KR 970003561A KR 1019950019098 A KR1019950019098 A KR 1019950019098A KR 19950019098 A KR19950019098 A KR 19950019098A KR 970003561 A KR970003561 A KR 970003561A
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KR
South Korea
Prior art keywords
forming
pattern
patterned
layer
fine pattern
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Application number
KR1019950019098A
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Korean (ko)
Inventor
최용근
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019098A priority Critical patent/KR970003561A/en
Publication of KR970003561A publication Critical patent/KR970003561A/en

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 노광장비의 렌즈 해상력과는 무관하게 패턴을 형성할 수 있는 미세 패턴 형성방법에 관한 것으로, 반도체 소자 제조공정 중 게이트 패턴을 형성하기 위한 방법에 있어서, 패턴형성하고자 하는 층을 증착하는 단계; 상기 패턴형성하고자 하는 층 상부에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각마스크로 사용하여 하부의 상기 패턴형성하고자 하는 층을 식각하여 1차 패턴을 형성하는 단계; 및 상기 1차패턴의 크기를 감소시키기 위해 가장자리 소정영역을 산화시키는 제2단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of forming a fine pattern that can form a pattern irrespective of the lens resolution of an exposure apparatus. ; Forming a photoresist pattern on the layer to be patterned; Forming a primary pattern by etching the lower layer to be patterned using the photoresist pattern as an etching mask; And a second step of oxidizing an edge predetermined area to reduce the size of the primary pattern.

Description

미세 패턴 형성방법Fine pattern formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1D도는 본 발명의 일실시예에 따른 미세 패턴 형성방법이 적용된 트랜지스터 형성과정을 나타내는 도면도.1D is a view showing a transistor forming process to which a fine pattern forming method according to an embodiment of the present invention is applied.

Claims (3)

반도체 소자 제조공정 중 게이트 패턴을 형성하기 위한 방법에 있어서, 패턴형성하고자 하는 층을 증착하는 단계; 상기 패턴형성하고자 하는 층 상부에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각마스크로 사용하여 하부의 상기 패턴형성하고자 하는 층을 식각하여 1차 패턴을 형성하는 단계; 및 상기 1차 패턴의 크기를 감소시키기 위해 가장자리 소정영역을 산화시키는 제2단계를 포함하여 이루어지는 것을 특징으로 하는 미세 패턴 형성방법.A method for forming a gate pattern during a semiconductor device manufacturing process, the method comprising: depositing a layer to be patterned; Forming a photoresist pattern on the layer to be patterned; Forming a primary pattern by etching the lower layer to be patterned using the photoresist pattern as an etching mask; And a second step of oxidizing an edge predetermined area to reduce the size of the primary pattern. 제1항에 있어서, 상기 게이트전극은 다결정실리콘막으로 이루어지는 것을 특징으로 하는 미세 패턴 형성방법.The method of claim 1, wherein the gate electrode is made of a polycrystalline silicon film. 제1항에 있어서, 상기 제2단계는 상기 제1단계 후 전체 상부에 산화막을 형성하여 상기 게이트전극의 노출된 가장자리를 산화시킴으로써 이루어지는 것을 특징으로 하는 미세 패턴 형성방법.The method of claim 1, wherein the second step is performed by oxidizing exposed edges of the gate electrode by forming an oxide film on the entire upper portion after the first step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019098A 1995-06-30 1995-06-30 Fine pattern formation method KR970003561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019098A KR970003561A (en) 1995-06-30 1995-06-30 Fine pattern formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019098A KR970003561A (en) 1995-06-30 1995-06-30 Fine pattern formation method

Publications (1)

Publication Number Publication Date
KR970003561A true KR970003561A (en) 1997-01-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019098A KR970003561A (en) 1995-06-30 1995-06-30 Fine pattern formation method

Country Status (1)

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KR (1) KR970003561A (en)

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