KR900002420A - Method of forming high concentration source region and capacitor surface region of semiconductor device using selective sidewall doping technique (SSWDT) - Google Patents

Method of forming high concentration source region and capacitor surface region of semiconductor device using selective sidewall doping technique (SSWDT) Download PDF

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Publication number
KR900002420A
KR900002420A KR1019880009182A KR880009182A KR900002420A KR 900002420 A KR900002420 A KR 900002420A KR 1019880009182 A KR1019880009182 A KR 1019880009182A KR 880009182 A KR880009182 A KR 880009182A KR 900002420 A KR900002420 A KR 900002420A
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South Korea
Prior art keywords
forming
layer
source region
silicon wafer
region
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KR1019880009182A
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Korean (ko)
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KR910006747B1 (en
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오상묵
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정몽헌
현대전자산업 주식회사
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Priority to KR1019880009182A priority Critical patent/KR910006747B1/en
Publication of KR900002420A publication Critical patent/KR900002420A/en
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Publication of KR910006747B1 publication Critical patent/KR910006747B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

Abstract

내용 없음No content

Description

선택적 측면벽 도핑기술(SSWDT)을 이용한 반도체 소자의 고농도 소스영역 및 캐패시터 표면영역 형성방법Method of forming high concentration source region and capacitor surface region of semiconductor device using selective sidewall doping technique (SSWDT)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 2c도는 본 발명의 고농도 소스영역 및 캐패시터 표면영역 형성방법을 설명하기 위한 도시도로서, 제1a도는 본 발명을 설명하기 위해 웨이퍼상에 마스크층을 형성한 후 포토레지스터층을 코팅한 상태의 단면도.1A to 2C are diagrams for explaining a method for forming a high concentration source region and a capacitor surface region of the present invention, and FIG. 1A is a view illustrating a photoresist layer after forming a mask layer on a wafer to illustrate the present invention. Section of status.

제1b도는 제1a도에서 포토레지스터층의 일부분을 제거한 상태의 단면도.FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG.

제1c도는 제1b도에서 마스크 패턴을 형성하고, 잔여 포토레지스터를 제거한 상태의 단면도.FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a residual photoresist removed.

제2a도는 제1c도의 공정후에 실리콘 웨이퍼를 소정깊이로 에칭한후 도프산화물을 침착하여 고열처리를 하는 공정을 도시한 단면도.FIG. 2A is a cross-sectional view showing a process of etching a silicon wafer to a predetermined depth after the process of FIG. 1C and then depositing dope oxide to perform high heat treatment.

제2b도는 제2a도의 열처리 공정후 에칭된 웨이퍼 깊이에 도핑영역이 형성되고, 도프산화물을 제거한 상태의 단면도.FIG. 2B is a cross sectional view showing a doped region formed at the depth of the etched wafer after the heat treatment process of FIG.

제2c도는 제2b도 상태에서 트렌치 에칭을 행하여 측면벽에 선택적으로 도핑된 소스영역이 형성된 상태의 단면도.FIG. 2C is a cross-sectional view of a trench etched in the FIG. 2B state to form a doped source region selectively on the sidewall.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 웨이퍼 2 : 산화물(OXIDE)1: Silicon Wafer 2: Oxide (OXIDE)

3 : 질화물(NITRIDE) 4 : 포토레지스터층(PHOTO-RESISTER LAYER)3: NITRIDE 4: Photo Register Layer (PHOTO-RESISTER LAYER)

5 : 도프산화물 6 : 도핑영역(소스영역)5: doped oxide 6: doped region (source region)

Claims (2)

메가 D RAM급 이상의 반도체 고집적 소자의 소스영역 형성방법에 있어서, 실리콘 웨이퍼 위에 산화물층을 침착하고 그위에 질화물층을 도핑하여 마스크층을 형성한 다음, 포토레지스터층을 코팅하는 공정과, 상기 포토레지스터층의 일정부분을 제거시켜 노출된 마스크층을 실리콘 표면까지 에칭하여 마스크 패턴을 형성하고, 사진식각법에 의해 마스크층 상부의 포토레지스터를 제거하는 공정과, 상기 마스크패턴 형성 공정후에노출된 실리콘 웨이퍼 부위를 에칭처리하는 공정과, 상기 마스크 패턴위에 도프산화물을 일정한 두께로 침착한후 고열처리하여 실리콘 웨이퍼 내부에 상기 물질이 주입되는 도핑영역을 형성하고, 상기 침착물질을 에칭처리로 제거하는 공정과, 상기 도핑영역의 좌우측면을 남기고 실리콘 웨이퍼에 트렌치 구조를 형성하는 공정으로 이루어지는 것을 특징으로 하는 선택적 측면벽 도핑기술을 이용한 반도체 소자의 소스영역 및 캐패시터 표면영역 형성방법.A method of forming a source region of a semiconductor high-density device of a mega D RAM or more type, comprising: depositing an oxide layer on a silicon wafer, doping a nitride layer thereon, forming a mask layer, and then coating a photoresist layer; Removing a portion of the layer to etch the exposed mask layer to the silicon surface to form a mask pattern, and removing the photoresist on the mask layer by photolithography; and exposing the silicon wafer after the mask pattern forming process. Etching a portion, depositing a dope oxide to a predetermined thickness on the mask pattern, and then performing a high heat treatment to form a doped region into which the material is injected into the silicon wafer, and removing the deposited material by etching. And forming a trench structure in the silicon wafer leaving left and right sides of the doped region. A method of forming a source region and a capacitor surface region of a semiconductor device using a selective sidewall doping technique, characterized in that consisting of a positive. 반도체 고집적소자에 있어서, 실리콘 웨이퍼상에 마스크 패턴을 형성시키고 구조를 형성하여 도프산화물 침착처리에 의해 상기 트랜치 구조의 상부 좌, 우측면 상부애 도핑영역인 소스영역을 가진 트랜치 캐패시커를 포함하는 것을 특징으로 하는 반도체 고집적소자.A semiconductor integrated device, comprising: a trench capacitor having a source region that is a doped region in the upper left and right sides of the trench structure by forming a mask pattern and forming a structure on a silicon wafer to form a dope oxide deposition process. A semiconductor highly integrated device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009182A 1988-07-22 1988-07-22 Semiconductor device source region and capacitor surface region forming method KR910006747B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880009182A KR910006747B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region and capacitor surface region forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880009182A KR910006747B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region and capacitor surface region forming method

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KR900002420A true KR900002420A (en) 1990-02-28
KR910006747B1 KR910006747B1 (en) 1991-09-02

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