KR900002426A - Source region formation method of semiconductor device using selective bottom surface doping technique - Google Patents

Source region formation method of semiconductor device using selective bottom surface doping technique Download PDF

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Publication number
KR900002426A
KR900002426A KR1019880009188A KR880009188A KR900002426A KR 900002426 A KR900002426 A KR 900002426A KR 1019880009188 A KR1019880009188 A KR 1019880009188A KR 880009188 A KR880009188 A KR 880009188A KR 900002426 A KR900002426 A KR 900002426A
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South Korea
Prior art keywords
source region
semiconductor device
formation method
region formation
surface doping
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KR1019880009188A
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Korean (ko)
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KR910006749B1 (en
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오상묵
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정몽헌
현대전자산업 주식회사
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Priority to KR1019880009188A priority Critical patent/KR910006749B1/en
Publication of KR900002426A publication Critical patent/KR900002426A/en
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Publication of KR910006749B1 publication Critical patent/KR910006749B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

선택적 하부면 도핑기술을 이용한 반도체소자의 소스영역 형성방법Source region formation method of semiconductor device using selective bottom surface doping technique

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제2d도는 본 발명의 소스영역 형성방법을 설명하기 위한 도시도로서, 제1a도는 본 발명을 설명하기 위해 웨이퍼상에 마스크 층을 형성한후 포토레지스터를 코팅한 상태의 단면도.1A to 2D are views for explaining a method of forming a source region of the present invention, and FIG. 1A is a cross-sectional view of a state in which a photoresist is coated after a mask layer is formed on a wafer to illustrate the present invention.

제1b도는 제1a도에서 포토레지스터층의 일부분을 제거한 상태의 단면도.FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG.

제1c도는 제1b도에서 마스크 패턴을 형성하고 포토레지스터를 제거한 상태의 단면도.FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a photoresist removed. FIG.

제2a도는 제1c도의 공정후에 트렌치 구조를 형성한 상태의 단면도.FIG. 2A is a cross-sectional view of a trench structure formed after the process of FIG. 1C. FIG.

제2b도는 제2a도의 트렌치 구조와 질화물층에 도프산화물을 침착한 상태의 단면도.FIG. 2B is a cross-sectional view of dope oxide deposited on the trench structure and nitride layer of FIG. 2A. FIG.

제2c도는 제2a도의 침착물을 일정부분만 남기고 제거하고 고열처리를 하는 공정을 도시한 단면도.FIG. 2C is a cross-sectional view illustrating a process of removing and depositing only a portion of the deposit of FIG.

제2d도는 제2c도의 열처리 공정후, 도프산화물을 제거한 다음 도핑된 소스영역이 형성된 상태의 단면도.FIG. 2D is a cross-sectional view of the doped source region formed after removing the dope oxide after the heat treatment process of FIG.

Claims (1)

메가 D RAM급 이상의 반도체 고집적소자의 소스영역 형성방법에 있어서, 실리콘 웨이퍼 위에 산화물층을 침착하고 그위에 질화물층을 도핑하여 마스크층을 형성한 다음, 포토레지스터를 코팅하는 공정과, 상기 마스크 패턴공정에 의해 노출된 실리콘웨이퍼상 트렌치 구조를 형성하는 공정과, 마스크층 상부의 질화물층과 트렌치내에 도프산화물을 침착하여 트렌치의 일정부분까지만 남기고 상기 침착물을 제거한 후 열처리하는공정과, 상기 열처리 공정후, 트렌치내의 침착물을 에칭기술에 의해 제거하는 공정으로 이루어지는 것을 특징으로 하는 반도체소자의 소스영역 형성방법.A method for forming a source region of a semiconductor high-integration device of a mega D RAM class or more, comprising: depositing an oxide layer on a silicon wafer, doping a nitride layer thereon, forming a mask layer, and then coating a photoresist; Forming a silicon wafer-like trench structure exposed by the step; And removing the deposits in the trenches by an etching technique. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009188A 1988-07-22 1988-07-22 Semiconductor device source region forming method KR910006749B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880009188A KR910006749B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880009188A KR910006749B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region forming method

Publications (2)

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KR900002426A true KR900002426A (en) 1990-02-28
KR910006749B1 KR910006749B1 (en) 1991-09-02

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KR1019880009188A KR910006749B1 (en) 1988-07-22 1988-07-22 Semiconductor device source region forming method

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KR910006749B1 (en) 1991-09-02

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