KR900002423A - Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device - Google Patents
Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device Download PDFInfo
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- KR900002423A KR900002423A KR1019880009185A KR880009185A KR900002423A KR 900002423 A KR900002423 A KR 900002423A KR 1019880009185 A KR1019880009185 A KR 1019880009185A KR 880009185 A KR880009185 A KR 880009185A KR 900002423 A KR900002423 A KR 900002423A
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Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 1A도 내지 제2B도는 본 발명의 소스영역 및 캐패시터 표면영역 혹은 전극영역 형성방법을 설명하기 위한 도시도로서, 제1A도는 본 발명을 설명하기 위해 N+기판에 에피텍셜 성장층을 형성시키고 그 위에 마스크층을 형성한 후 포토레지스터층을 코팅한 상태의 단면도. 제1B도는 제1A도에서 포토레지스터층의 일부분을 제거한 상태의 단면도. 제1C도는 제1B도에서 마스크 패턴을 형성하고 마스크층 상부의 포토레지스터층을 제거한 상태의 단면도.1A to 2B are diagrams for explaining a method for forming a source region and a capacitor surface region or an electrode region of the present invention, and FIG. 1A shows an epitaxial growth layer formed on an N + substrate to explain the present invention. A cross-sectional view of a state in which a photoresist layer is coated after the mask layer is formed thereon. FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG. FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a photoresist layer on the mask layer removed.
제 2A도는 제1C도의 트랜치를 형성하고 도프산화물을 침착한 다음 고열처리하는 공정을 도시한 단면도. 제2B도는 제2A도의 열처리 공정후 트랜치 구조의 내부에 도피영역이 형성되고 도프산화물을 제거한 상태의 단면도.FIG. 2A is a cross sectional view showing a process of forming the trench of FIG. 1C, depositing dope oxide, and then performing high heat treatment. FIG. FIG. 2B is a cross-sectional view of a state in which a doped region is formed inside the trench structure after the heat treatment process of FIG.
제3도는 본 발명의 일 실시예를 N+기판상에 에픽텍셜 성장층과 겹치도록 트랜치 구조를 형성시켜 도핑된 소스영역이 형성된 상태의 단면도.3 is a cross-sectional view of an embodiment of the present invention in which a doped source region is formed by forming a trench structure on an N + substrate so as to overlap an epitaxial growth layer.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019880009185A KR900002423A (en) | 1988-07-22 | 1988-07-22 | Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019880009185A KR900002423A (en) | 1988-07-22 | 1988-07-22 | Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device |
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KR900002423A true KR900002423A (en) | 1990-02-28 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019880009185A KR900002423A (en) | 1988-07-22 | 1988-07-22 | Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device |
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KR (1) | KR900002423A (en) |
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1988
- 1988-07-22 KR KR1019880009185A patent/KR900002423A/en not_active Application Discontinuation
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