KR900002423A - Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device - Google Patents

Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device Download PDF

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Publication number
KR900002423A
KR900002423A KR1019880009185A KR880009185A KR900002423A KR 900002423 A KR900002423 A KR 900002423A KR 1019880009185 A KR1019880009185 A KR 1019880009185A KR 880009185 A KR880009185 A KR 880009185A KR 900002423 A KR900002423 A KR 900002423A
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South Korea
Prior art keywords
layer
forming
source region
trench structure
trench
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KR1019880009185A
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Korean (ko)
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오상묵
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정몽헌
현대전자산업 주식회사
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Priority to KR1019880009185A priority Critical patent/KR900002423A/en
Publication of KR900002423A publication Critical patent/KR900002423A/en

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Abstract

내용 없음No content

Description

반도체 소자의 소스영역 및 캐피시터 표면영역 형성방법 및 그 반도체 집적 소자Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1A도 내지 제2B도는 본 발명의 소스영역 및 캐패시터 표면영역 혹은 전극영역 형성방법을 설명하기 위한 도시도로서, 제1A도는 본 발명을 설명하기 위해 N+기판에 에피텍셜 성장층을 형성시키고 그 위에 마스크층을 형성한 후 포토레지스터층을 코팅한 상태의 단면도. 제1B도는 제1A도에서 포토레지스터층의 일부분을 제거한 상태의 단면도. 제1C도는 제1B도에서 마스크 패턴을 형성하고 마스크층 상부의 포토레지스터층을 제거한 상태의 단면도.1A to 2B are diagrams for explaining a method for forming a source region and a capacitor surface region or an electrode region of the present invention, and FIG. 1A shows an epitaxial growth layer formed on an N + substrate to explain the present invention. A cross-sectional view of a state in which a photoresist layer is coated after the mask layer is formed thereon. FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG. FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a photoresist layer on the mask layer removed.

제 2A도는 제1C도의 트랜치를 형성하고 도프산화물을 침착한 다음 고열처리하는 공정을 도시한 단면도. 제2B도는 제2A도의 열처리 공정후 트랜치 구조의 내부에 도피영역이 형성되고 도프산화물을 제거한 상태의 단면도.FIG. 2A is a cross sectional view showing a process of forming the trench of FIG. 1C, depositing dope oxide, and then performing high heat treatment. FIG. FIG. 2B is a cross-sectional view of a state in which a doped region is formed inside the trench structure after the heat treatment process of FIG.

제3도는 본 발명의 일 실시예를 N+기판상에 에픽텍셜 성장층과 겹치도록 트랜치 구조를 형성시켜 도핑된 소스영역이 형성된 상태의 단면도.3 is a cross-sectional view of an embodiment of the present invention in which a doped source region is formed by forming a trench structure on an N + substrate so as to overlap an epitaxial growth layer.

Claims (3)

메가 D RAM급 이상의 반도체 고집적 소자의 소스영역 형성방법에 있어서, N+(혹은 P+) 기판위에 에피텍셜 성장층을 형성시키고 그 위에 산화물층을 침착하고 그위에 질화물층을 도핑하여 마스크층을 형성한 다음, 포토레지스터를 코팅하는 공정과, 상기 포토레지스터의 일정부분을 제거시켜 노출된 마스크층을 에피텍셜 표면까지 에칭하여 마스크 패턴을 형성하고 잔여 포토레지스터층을 제거하는 공정과 상기 마스크 패턴 형성 공정에서 표출된 에피텍셜 성창층(7)상에 트랜치 구조상에 형성하는 공정과, 상기 질화물층 트랜치 구조를 도프산화물을 일정한 두께로 침착한 후 고열처리하여 에피텍셜 성장층 내부에 상기 물질이 주입되는 도핑영역을 형성하고 상기 침착물질을 에칭처리로 제거하는 공정으로 이루어지는 것을 특징으로 하는 도핑기술을 이용한 반도체 소자의 소스영역 형성방법.In the method of forming a source region of a semiconductor high-density device of mega D RAM or more, an epitaxial growth layer is formed on an N + (or P + ) substrate, an oxide layer is deposited thereon, and a nitride layer is doped thereon to form a mask layer. Next, a process of coating the photoresist, removing a portion of the photoresist to etch the exposed mask layer to the epitaxial surface to form a mask pattern and to remove the remaining photoresist layer and the mask pattern forming process Forming a trench structure on the epitaxial layer formed on the epitaxial layer 7, and depositing a dope oxide to a predetermined thickness and then performing high heat treatment to inject the material into the epitaxial growth layer. Doping techniques comprising forming a region and removing the deposited material by etching. Source region formation method of a semiconductor device using. 반도체 집적소자에 있어서, 에피텍셜 성장층 상에 마스크 패턴을 형성시키고 트랜치 구조를 형성하여 트랜치 내벽전체에 도핑영역인 소스영역을 가진 트랜치 캐패시터를 포함하는 것을 특징으로 하는 반도체 집적 소자.A semiconductor integrated device, comprising: a trench capacitor having a source region serving as a doping region in the entire trench inner wall by forming a mask pattern on the epitaxial growth layer and forming a trench structure. 제2항에 있어서, 상기 트랜치 구조가 에피텍셜 성장층을 포함하여, 도프산화물 침착처리에 의해 트랜치 구조의 좌우측면과 하부에 도핑된 소스영역이 기판 상부와 겹치도록 길게 구성된 트랜치 캐패시터를 포함하는 것을 특징으로 하는 반도체 집적소자.The trench structure of claim 2, wherein the trench structure includes an epitaxial growth layer, and the trench structure includes a trench capacitor configured to have a source region doped on the left and right sides and a bottom of the trench structure overlapped with an upper portion of the substrate by a dope oxide deposition process. A semiconductor integrated device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009185A 1988-07-22 1988-07-22 Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device KR900002423A (en)

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KR1019880009185A KR900002423A (en) 1988-07-22 1988-07-22 Source region and capacitor surface region formation method of semiconductor device and semiconductor integrated device

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