KR930008647B1 - Shallow junction forming method of high integrated circuit - Google Patents

Shallow junction forming method of high integrated circuit Download PDF

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Publication number
KR930008647B1
KR930008647B1 KR1019900016276A KR900016276A KR930008647B1 KR 930008647 B1 KR930008647 B1 KR 930008647B1 KR 1019900016276 A KR1019900016276 A KR 1019900016276A KR 900016276 A KR900016276 A KR 900016276A KR 930008647 B1 KR930008647 B1 KR 930008647B1
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South Korea
Prior art keywords
shallow junction
hto
polysilicon
metal
forming
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KR1019900016276A
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Korean (ko)
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KR920008896A (en
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서광하
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금성일렉트론 주식회사
문정환
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Priority to KR1019900016276A priority Critical patent/KR930008647B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The method is executed by the steps of forming a gate, dielectrics, polysilicon layers on a predetermined portion of a semiconductor substrate, and forming a buried contact, depositing an HTO over the buried contact portion and the upper dielectric and performing ion-implantation after a P/R masking process to form a shallow junction, removing the exposed HTO portion via a wet etching and removing the P/R, and cleaning the buried contact by means of HF to deposit a metal, thereby alleviating the damage on the surface of the substrate during the ion implantation, inhibiting the ion penetration deeply into the substrate to obtain a desired shallow junction, and stabbly maintaining the interval between the polysilicon and metal to prevent the contact between them.

Description

고집적 소자의 셀로우 정크션 형성방법Cell Junction Formation Method for Highly Integrated Devices

제 1 도는 종래 고집적 소자의 단면도.1 is a cross-sectional view of a conventional highly integrated device.

제 2 도는 본 발명의 공정순서를 나타낸 단면도.2 is a cross-sectional view showing the process sequence of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 게이트1 substrate 2 gate

3,7 : 유전체 4 : 폴리실리콘3,7 dielectric 4: polysilicon

5 : 노드용 폴리실리콘 6 : 플레이트용 폴리실로콘5: polysilicon for nodes 6: polysilicon for plates

8 : HTO 9 : P/R8: HTO 9: P / R

10 : 셀로우 정크션 11 : 메탈10: Cell Junction 11: Metal

본 발명은 16M디램 이상의 고집적 소자의 셀러우 정크션(shallow Junction) 형성방법에 관한 것으로, HTO막을 이용하여 메탈콘택의 셀로우 정크션을 형성하고 플레이트용 폴리실리콘과 메탈사이의 접촉을 방지하는데 적합하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a shallow junction of a highly integrated device of 16M DRAM or more, and is suitable for forming a shallow junction of a metal contact using an HTO film and preventing contact between a polysilicon for a plate and a metal. I did it.

종래에는 고집적소자 제조시 여러 공정을 수행하는 동안 메탈콘택 영역에서의 증가된 저항을 감소시키기 위해 셀로우 정크션을 형성하였으며, 제 1 도에 도시된 바와같이 기판(1) 위에 게이트(2)를 형성하고 유전체(3)를 형성한 후 폴리실리콘(4), 노드용 폴리실리콘(5), 플레이트용 폴리실리콘(6), 유전체(7)를 차례로 형성한 상태에서 메몰콘택을 형성하여 에디셔널 이온주입(Additional ion implantation)하므로 셀로우 정크션(10) 영역을 형성하였으며, 이후 메탈(11)을 증착하였다.Conventionally, a shallow junction has been formed to reduce the increased resistance in the metal contact region during various processes in the fabrication of highly integrated devices, and as shown in FIG. 1, the gate 2 is formed on the substrate 1. After forming the dielectric 3, a mem contact is formed in a state in which polysilicon 4, node polysilicon 5, plate polysilicon 6, and dielectric 7 are sequentially formed. Implantation (Additional ion implantation) was formed to form a shallow junction (10) region, and then the metal (11) was deposited.

그러나, 상기 종래기술에 있어서는 기판(1)표면에 직접 이온을 주입하여 기판의 콘택표면이 손상되기 쉽고 이온이 깊게 주입될 경우 셀로우 정크션(10)을 유지하기가 어려웠다.However, in the above prior art, it is difficult to maintain the shallow junction 10 when ions are directly injected to the surface of the substrate 1 and the contact surface of the substrate is easily damaged.

또한, 플레이트용 폴리실리콘(6)과 메탈(11)사이의 간격이 너무 좁아서 플레이트용 폴리실리콘(6)과 메탈(11)간에 접촉이 발생하기 쉬웠다.In addition, the gap between the plate polysilicon 6 and the metal 11 was so narrow that contact between the plate polysilicon 6 and the metal 11 was likely to occur.

본 발명은 이와같은 종래기술의 문제점을 해결하기 위한 것으로 이하에서 첨부된 도면 제 2 도에 의하여 상세히 설명하면 다음과 같다.The present invention is to solve the problems of the prior art described in detail with reference to the accompanying drawings, the second drawing as follows.

먼저 제 2a 도와 같이 기판(1) 위에 게이트(2), 유전체(3), 폴리 실리콘(4), 노드용 폴리실리콘(5), 플레이트용 폴리실리콘(6), 유전체(7)를 기존의 방법에 의해 차례로 형성한 후 매몰콘택을 형성한다.First, the gate 2, the dielectric 3, the polysilicon 4, the polysilicon 5 for the node, the polysilicon 6 for the plate, and the dielectric 7 are formed on the substrate 1 as shown in FIG. 2A. After forming sequentially by, a buried contact is formed.

그리고 HTO(High Temperature Oxide ; 고온산화막)(8)를 상기 결과 물 전면에 약 500Å정도 증착하고, P/R(9)을 사용하여 마스킹 작업을 한 후 이온을 주입하므로서 셀로우 정크션(10)을 형성한다.And the HTO (High Temperature Oxide) (8) is deposited on the surface of the water about 500Å, the masking operation using the P / R (9) after the implantation of the cell juncture (10) To form.

다음에 제 2b 도와 같이 습식식각에 의해 노출된 HTO(8)를 제거하고 P/R(9)을 제거한다. 이어서 제 2c 도와 같이 HF용액으로 콘택부분을 세척한 후 메탈(11)을 증착한다.Next, as shown in FIG. 2B, the HTO 8 exposed by wet etching is removed and the P / R 9 is removed. Subsequently, the contact portion is washed with HF solution as shown in FIG. 2C and then the metal 11 is deposited.

이와같은 본 발명의 공정에 의하면 콘택표면에 증착된 HTO(8)에 의해 이온주입시 기판(1) 표면이 손상되는 것을 완화시킬 수 있으며, 이온이 기판(1)으로 깊숙이 들어가는 것을 방지할 수 있어 원하는 셀로우 정크션을 얻을 수 있다.According to the process of the present invention as described above it is possible to mitigate the damage to the surface of the substrate 1 during ion implantation by the HTO (8) deposited on the contact surface, it is possible to prevent the ions from going deep into the substrate (1) You can get the desired throw junction.

또한, HTO(8)에 의하여 플레이트용 폴리실리콘(6)과 메탈(11) 사이의 간격이 안전하게 유지되므로 폴리실리콘(6)과 메탈(11)사이의 접촉을 방지할 수 있는 효과가 있다.In addition, the gap between the polysilicon 6 for the plate and the metal 11 is safely maintained by the HTO 8, thereby preventing contact between the polysilicon 6 and the metal 11.

Claims (2)

반도체 기판(1)위에 게이트(2), 유전체(3,7), 폴리실리콘층(4,5,6)등을 소정부위에 형성하고 매몰콘택을 형성하는 공정과, 상기 매몰콘택부위와 최상층의 유전체(7)에 걸쳐 HTO(8)를 증착하고 P/R마스킹 작업 후 이온주입을 실시하여 셀로우 정크션(10)을 형성하는 공정과, 노출된 HTO부분을 습식식각에 의해 제거하고 이어 P/R을 제거하는 공정과, HF로 매몰콘택을 세척한 후 메탈을 증착하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 고집적 소자의 셀로우 정크션 형성방법.Forming gates 2, dielectrics 3,7, polysilicon layers 4, 5, 6, etc. on predetermined portions on the semiconductor substrate 1, and forming an investment contact; Depositing HTO (8) over the dielectric (7) and ion implantation after P / R masking to form a shallow junction (10), and removing the exposed HTO by wet etching, followed by P A method of forming a shallow junction of a highly integrated device, characterized in that the step of removing the / R, and the step of washing the buried contact with HF and then depositing a metal. 제 1 도에 있어서, HTO는 500Å정도 증착함을 특징으로 하는 고집적 소자의 셀로우 정크션 형성방법.The method of claim 1, wherein HTO is deposited to about 500 GPa.
KR1019900016276A 1990-10-13 1990-10-13 Shallow junction forming method of high integrated circuit KR930008647B1 (en)

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Application Number Priority Date Filing Date Title
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KR930008647B1 true KR930008647B1 (en) 1993-09-11

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