KR920008896A - Cell Junction Formation Method for Highly Integrated Devices - Google Patents

Cell Junction Formation Method for Highly Integrated Devices Download PDF

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Publication number
KR920008896A
KR920008896A KR1019900016276A KR900016276A KR920008896A KR 920008896 A KR920008896 A KR 920008896A KR 1019900016276 A KR1019900016276 A KR 1019900016276A KR 900016276 A KR900016276 A KR 900016276A KR 920008896 A KR920008896 A KR 920008896A
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KR
South Korea
Prior art keywords
highly integrated
formation method
forming
integrated devices
junction formation
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Application number
KR1019900016276A
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Korean (ko)
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KR930008647B1 (en
Inventor
서광하
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문정환
금성일렉트론 주식회사
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Priority to KR1019900016276A priority Critical patent/KR930008647B1/en
Publication of KR920008896A publication Critical patent/KR920008896A/en
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Publication of KR930008647B1 publication Critical patent/KR930008647B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

고집적 소자의 셀로우 정크션 형성방법Cell Junction Formation Method for Highly Integrated Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본발명의 공정순서를 나타낸 단면도2 is a cross-sectional view showing the process sequence of the present invention.

Claims (2)

통상의 방법에 의해 기판위에 게이트, 유전체, 폴리실콘등을 형성하고 메몰콘택을 형성하는 공정과, 상기 매몰콘택부위와 최상층의 유전체에 걸쳐 HTO 를 증착하고 P/R마스킹 작업후 이온주입을 실시하여 셀로우 정크션을 형성하는 공정과, HF로 매몰콘택을 세척한 후 메탈을 증착하는 공정을 차례로 실시하여서 이루어짐을 특징으로하는 고집직소자의 셀로우 정크션 형성방법.Forming a gate, dielectric, polysilicon, etc. on the substrate by a conventional method, and forming a buried contact, depositing HTO over the buried contact portion and the dielectric of the uppermost layer, and ion implanting after P / R masking operation A method of forming a shallow junction of a highly integrated device, characterized in that it is performed by sequentially performing a process of forming a shallow junction, and a process of depositing a metal after washing the investment contact with HF. 제1항에 있어서, HTO는 500A정도 증착함을 특징으로하는 고집적 소자의 셀로우 정크션 형성방법.The method of claim 1, wherein the HTO is deposited to about 500A. ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900016276A 1990-10-13 1990-10-13 Shallow junction forming method of high integrated circuit KR930008647B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900016276A KR930008647B1 (en) 1990-10-13 1990-10-13 Shallow junction forming method of high integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900016276A KR930008647B1 (en) 1990-10-13 1990-10-13 Shallow junction forming method of high integrated circuit

Publications (2)

Publication Number Publication Date
KR920008896A true KR920008896A (en) 1992-05-28
KR930008647B1 KR930008647B1 (en) 1993-09-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016276A KR930008647B1 (en) 1990-10-13 1990-10-13 Shallow junction forming method of high integrated circuit

Country Status (1)

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KR (1) KR930008647B1 (en)

Also Published As

Publication number Publication date
KR930008647B1 (en) 1993-09-11

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