KR910005385A - How to Form Symmetric Parabolic Junctions - Google Patents

How to Form Symmetric Parabolic Junctions Download PDF

Info

Publication number
KR910005385A
KR910005385A KR1019890012083A KR890012083A KR910005385A KR 910005385 A KR910005385 A KR 910005385A KR 1019890012083 A KR1019890012083 A KR 1019890012083A KR 890012083 A KR890012083 A KR 890012083A KR 910005385 A KR910005385 A KR 910005385A
Authority
KR
South Korea
Prior art keywords
parabolic
forming
source
gate
drain
Prior art date
Application number
KR1019890012083A
Other languages
Korean (ko)
Other versions
KR0136918B1 (en
Inventor
라사균
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019890012083A priority Critical patent/KR0136918B1/en
Publication of KR910005385A publication Critical patent/KR910005385A/en
Application granted granted Critical
Publication of KR0136918B1 publication Critical patent/KR0136918B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

대칭적 포물선 정션 형성 방법How to Form Symmetric Parabolic Junctions

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가)-(마)는 본 발명에 따른 대칭적 포물선 소오스/드레인 정선 형성 방법 공정도.2 (a)-(e) are process diagrams for forming a symmetrical parabolic source / drain liner according to the present invention.

Claims (1)

게이트 옥시데이션 작업을 한후 “폴리 실리콘+LTO 디포지션” 작업을 하는 공정과, 상기 공정후 게이트 매스크 작업 및 게이트 형성을 위한 에치 작업을 하는 공정과, 상기 게이트 형성을 위한 에치 작업후 소오스/드레인 매스크 작업을 하는 공정과, 상기 소오스/드레인 매스크 공정후 딜트이온 임플란트 하고 180°회전하여 틸트이온 임플란트를 하여 대칭적 포물선 소오스/드레인을 형성하는 공정과, 상기 대칭적 포물선 소오스/드레인을 형성 공정후 디퓨전 작업을 하고 대칭적 포물선 정션을 위해 실리콘 습식 에치를 하는 공정을 포함하여 구성됨으로서 캐패시터 형성시 배리드 콘텍 지역의 대칭적 포물선 정션에 의해 캐패시턴스가 증가하도록 한 것을 특징으로 하는 대칭적 포물선 정션 형성 방법.A process of performing “polysilicon + LTO deposition” after a gate oxidization operation, a process of etching the gate mask and a gate formation after the process, and a source / drain mask after the etching operation to form the gate A process of working, a process of forming a symmetric parabolic source / drain by forming a tilt ion implant by rotating the tilt ion implant after the source / drain mask process, and rotating the tilt ion by 180 °, and the process of forming the symmetric parabolic source / drain after the process of diffusion A method of forming a symmetrical parabolic junction, comprising a process of working and performing a silicon wet etch for a symmetrical parabolic junction, such that the capacitance is increased by a symmetrical parabolic junction in the buried contact area during capacitor formation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890012083A 1989-08-24 1989-08-24 Semiconductor device having symmetrical parabolic junction KR0136918B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890012083A KR0136918B1 (en) 1989-08-24 1989-08-24 Semiconductor device having symmetrical parabolic junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890012083A KR0136918B1 (en) 1989-08-24 1989-08-24 Semiconductor device having symmetrical parabolic junction

Publications (2)

Publication Number Publication Date
KR910005385A true KR910005385A (en) 1991-03-30
KR0136918B1 KR0136918B1 (en) 1998-04-29

Family

ID=19289214

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890012083A KR0136918B1 (en) 1989-08-24 1989-08-24 Semiconductor device having symmetrical parabolic junction

Country Status (1)

Country Link
KR (1) KR0136918B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412129B1 (en) * 2001-04-30 2003-12-31 주식회사 하이닉스반도체 Method for forming junction in semiconductor device
KR20030091533A (en) * 2002-05-28 2003-12-03 삼성전자주식회사 MOS transistor having source/drain of triangle-type impurity doping profile and fabrication method thereof

Also Published As

Publication number Publication date
KR0136918B1 (en) 1998-04-29

Similar Documents

Publication Publication Date Title
KR910005385A (en) How to Form Symmetric Parabolic Junctions
KR910008865A (en) Slop Potential MOSFET Manufacturing Method
KR890005893A (en) Manufacturing Method of Semiconductor Device
KR910005441A (en) Buried contact formation method using silicide
KR910001930A (en) Self-aligned Low Doped Junction Formation Method
KR940008097A (en) Semiconductor memory cell manufacturing method with increased capacitor capacity
KR960036145A (en) Highly Integrated Thin Film Transistors and Manufacturing Method Thereof
KR920008896A (en) Cell Junction Formation Method for Highly Integrated Devices
KR910015060A (en) Method of manufacturing CCD channel using magnetic alignment
KR960035918A (en) Shallow Junction Formation Method of Semiconductor Devices
KR910005455A (en) Capacitor electrode formation method
KR910019204A (en) LDD manufacturing method using slop gate
KR920007098A (en) Method of manufacturing insulated gate field effect transistor
KR910013509A (en) A method of connecting a capacitor and a source using sidewall oxide
KR910013426A (en) DRAM manufacturing method
KR970030917A (en) Method of manufacturing thin film transistor
KR970077364A (en) Semiconductor device manufacturing method
KR950021111A (en) Source contact formation method of semiconductor device
KR980005881A (en) Method of manufacturing semiconductor device
KR930005243A (en) Structure and manufacturing method of transistor using shallow junction
KR920013775A (en) Trench using transistor manufacturing method
KR930015055A (en) MOS transistor manufacturing method
KR910013550A (en) High capacity stack cell manufacturing method
KR930015081A (en) Shallow Bonded MOSFET Manufacturing Method
KR910017635A (en) Memory Cell Capacitor Manufacturing Method

Legal Events

Date Code Title Description
E902 Notification of reason for refusal
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091222

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee