KR930015055A - MOS transistor manufacturing method - Google Patents

MOS transistor manufacturing method Download PDF

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Publication number
KR930015055A
KR930015055A KR1019910022833A KR910022833A KR930015055A KR 930015055 A KR930015055 A KR 930015055A KR 1019910022833 A KR1019910022833 A KR 1019910022833A KR 910022833 A KR910022833 A KR 910022833A KR 930015055 A KR930015055 A KR 930015055A
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KR
South Korea
Prior art keywords
forming
trench
oxide film
region
gate
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Application number
KR1019910022833A
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Korean (ko)
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KR940010921B1 (en
Inventor
김성식
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문정환
금성일렉트론 주식회사
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Priority to KR1019910022833A priority Critical patent/KR940010921B1/en
Publication of KR930015055A publication Critical patent/KR930015055A/en
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Publication of KR940010921B1 publication Critical patent/KR940010921B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

MOS 트랜지스터 제조방법MOS transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 종래의 MOS 트랜지스터 구성도.1 is a configuration diagram of a conventional MOS transistor.

제 2a 도는 종래의 LDD 구조도 및 메탈 단차피복 형태 도시도.Figure 2a is a diagram of a conventional LDD structure and metal step coating form.

제 2b 도는 본 발명의 MOS 트랜지스터 구성도.2b is a block diagram of a MOS transistor of the present invention.

제 3 도는 본 발명의 MOS 트랜지스터 제조공정도.3 is a MOS transistor manufacturing process diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 실리폰 기판 12 : P-영역11: Siphone Substrate 12: P - Area

13 : P+영역 14 : n-영역13: P + region 14: n - region

15 : N+영역 16 : 산화막15: N + region 16: oxide film

17 : 폴리실리콘 18 : BPSG17: polysilicon 18: BPSG

19 : 텅스텐19: tungsten

Claims (1)

MOS 트랜지스터 제조방법에 있어서, 실리콘 기판에서 필드 산화막이 형성될 자리에 1차 트렌치를 쌍으로형성하여 트랜치 사이에 활성영역을 만들고, 그 활성 영역의 하부는 1차 웰 공정으로 p-영역을 형성하고 활성영역의 상부는 2차웰 공정으로 p+영역을 형성하여 2중 웰 구조를 형성하는 단계(a)와, 1차 트랜치 쌍 사이의 활성영역에 게이트 용으로 2차 트랜치를 형성하고, 1차 트랜치와 2차 트랜치 사이에 이온 주입 공정을 거쳐 2차 트랜치 측벽의 기판 하부에는 n-영역을 형성하고 상기 기판 상부에는 n+영역이 형성되도록 하므로 LDD 구조를 갖는 소스/드레인을 형성하는 단계(b)와, 1차 트랜치 내부에는 산화막을 형성하여 필드 산화막을 만들고, 2차 트랜치는 트랜치 내부에 산화막을 얇게 형성하여 게이트 산화막을 형성하며 그 위에 폴리실리콘을 데포지션하여 게이트를 형성하는 단계(C)와, BPSG 공정을 실시하고 소스/드레인 부와 게이트부에 콘택을 낸 후, 메탈 공정을 실시하며, 문턱전압 조절용 이온 주입을 실시하는 단계(d)를 포함하여 이루어지는 MOS 트랜지스터 제조방법.In the method of manufacturing a MOS transistor, a pair of primary trenches are formed in a place where a field oxide film is to be formed in a silicon substrate to form an active region between trenches, and the lower portion of the active region forms a p − region by a first well process. The upper portion of the active region is formed by forming a p + region by a secondary well process to form a double well structure (a), forming a secondary trench for the gate in the active region between the primary trench pairs, and forming a primary trench. (B) forming a source / drain having an LDD structure by forming an n − region under the substrate of the secondary trench sidewall and forming an n + region on the substrate through an ion implantation process between the and second trenches. And an oxide film is formed inside the first trench to form a field oxide film, and the second trench forms a gate oxide film by forming a thin oxide film inside the trench, and a polysilicon layer is formed thereon. Position (C) to form a gate, performing a BPSG process, contacting the source / drain portion and the gate portion, performing a metal process, and performing ion implantation for adjusting the threshold voltage (d). MOS transistor manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910022833A 1991-12-13 1991-12-13 Manufacturing method of mosfet KR940010921B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910022833A KR940010921B1 (en) 1991-12-13 1991-12-13 Manufacturing method of mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910022833A KR940010921B1 (en) 1991-12-13 1991-12-13 Manufacturing method of mosfet

Publications (2)

Publication Number Publication Date
KR930015055A true KR930015055A (en) 1993-07-23
KR940010921B1 KR940010921B1 (en) 1994-11-19

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ID=19324712

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910022833A KR940010921B1 (en) 1991-12-13 1991-12-13 Manufacturing method of mosfet

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KR (1) KR940010921B1 (en)

Also Published As

Publication number Publication date
KR940010921B1 (en) 1994-11-19

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