KR910008865A - Slop Potential MOSFET Manufacturing Method - Google Patents

Slop Potential MOSFET Manufacturing Method Download PDF

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Publication number
KR910008865A
KR910008865A KR1019890015222A KR890015222A KR910008865A KR 910008865 A KR910008865 A KR 910008865A KR 1019890015222 A KR1019890015222 A KR 1019890015222A KR 890015222 A KR890015222 A KR 890015222A KR 910008865 A KR910008865 A KR 910008865A
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KR
South Korea
Prior art keywords
gate
slop
oxide
potential
photoresist
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Application number
KR1019890015222A
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Korean (ko)
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KR0151124B1 (en
Inventor
박용
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문정환
금성일렉트론 주식회사
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Priority to KR1019890015222A priority Critical patent/KR0151124B1/en
Publication of KR910008865A publication Critical patent/KR910008865A/en
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Publication of KR0151124B1 publication Critical patent/KR0151124B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

내용 없음No content

Description

슬롭 포텐셜 MOSFET 제조방법Slop Potential MOSFET Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (a)~(c)는 종래의 MOSFET 제조공정도.1 (a) to (c) are conventional MOSFET manufacturing process diagrams.

제2도 (a)~(d)는 본 발명에 따른 슬롭 포텐셜 MOSFET 제조공정도.Figure 2 (a) to (d) is a manufacturing process diagram of a slop potential MOSFET according to the present invention.

Claims (1)

실리콘기판(1)상에 버퍼 옥사이드(2)를 형성한 후 포토 레지스트(7)ㄹ 매스킹하는 단계와, 상기 포토레지스터(7) 매스킹단계후 습식에치를 하여 버퍼 옥사이드(2)가 경사지도록 하는 단계와, 상기 버퍼 옥사이드(2)를 경사지도록 하는 단계후 포토레지스터(7)를 제거하는 채널이온 임플란트(CH I/I)를 하는 단계와, 상기 채널이온 임플란드(CH I/I)를 한후 버퍼 옥사이드(2)를 제거하고 게이트 옥사이드(3)를 형성하는 단계와, 상기 게이트 옥사이드(3) 형성단계후 폴리실리콘(4)을 증착한 다음 게이트 옥사이드(3)와 폴리실리콘(4)을 에칭하여 게이트를 형성하는 소오스(5)와 드레인(6)을 형성하는 단계를 포함하는 게이트아래 포텐셜이 경사지도록 한 것을 특징으로 하는 습롭 포텐셜 MOSFET 제조방법.After forming the buffer oxide (2) on the silicon substrate (1) and masking the photoresist (7), and wet etching after the photoresist (7) masking step so that the buffer oxide (2) is inclined And a channel ion implant (CH I / I) for removing the photoresist (7) after the step of tilting the buffer oxide (2), and the channel ion implant (CH I / I). After removing the buffer oxide (2) to form a gate oxide (3), after the step of forming the gate oxide (3) is deposited polysilicon (4) and then the gate oxide (3) and polysilicon (4) A method for manufacturing a wet potential MOSFET, characterized in that the potential under the gate is inclined including etching a source (5) and a drain (6) to form a gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890015222A 1989-10-23 1989-10-23 Slope potential mosfet KR0151124B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890015222A KR0151124B1 (en) 1989-10-23 1989-10-23 Slope potential mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015222A KR0151124B1 (en) 1989-10-23 1989-10-23 Slope potential mosfet

Publications (2)

Publication Number Publication Date
KR910008865A true KR910008865A (en) 1991-05-31
KR0151124B1 KR0151124B1 (en) 1998-10-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015222A KR0151124B1 (en) 1989-10-23 1989-10-23 Slope potential mosfet

Country Status (1)

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KR (1) KR0151124B1 (en)

Also Published As

Publication number Publication date
KR0151124B1 (en) 1998-10-01

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