KR920015437A - MOS transistor - Google Patents

MOS transistor Download PDF

Info

Publication number
KR920015437A
KR920015437A KR1019910000557A KR910000557A KR920015437A KR 920015437 A KR920015437 A KR 920015437A KR 1019910000557 A KR1019910000557 A KR 1019910000557A KR 910000557 A KR910000557 A KR 910000557A KR 920015437 A KR920015437 A KR 920015437A
Authority
KR
South Korea
Prior art keywords
oxide
polysilicon
gate
forming
sidewalls
Prior art date
Application number
KR1019910000557A
Other languages
Korean (ko)
Other versions
KR940002777B1 (en
Inventor
한석우
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000557A priority Critical patent/KR940002777B1/en
Publication of KR920015437A publication Critical patent/KR920015437A/en
Application granted granted Critical
Publication of KR940002777B1 publication Critical patent/KR940002777B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

MOS 트랜지스터MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)~(바)는 본 발명에 따른 GOLD 구조의 MOS 트랜지스터 제조공정도.2A to 2B are MOS transistor manufacturing process diagrams of the GOLD structure according to the present invention.

Claims (1)

실리콘기판에 게이트옥사이드와 제1게이트 폴리실리콘과 제1옥사이드와 제2게이트 폴리실리콘과 제2옥사이드를 차례로 형성시켜 게이트 패턴을 형성하는 공정과, 제2옥사이드와 제2게이트 폴리실리콘과 제1옥사이드의 소오스/드레인 부분만을 식각한 후 M-이온을 주입하여 N-영역을 형성하는 공정과, 사이드월용 폴리실리콘을 형성시키는 공정과, 사이드월용 폴리실리콘과 제 1게이트 폴리실리콘을 식각하여 제1게이트 폴리실리콘과 제2게이트 폴리실리콘을 전기적으로 연결하는 폴리실리콘 사이드월을 형성시키는 공정과, 사이드월용 옥사이드를 형성시키는 공정과, 사이드월을 옥사이드와 게이트 옥사이드를 식각하여 게이트와 소오스/드레인을 분리하고 오버랩을 줄일 수 있도록 하는 옥사이드 사이드 월을 형성한 다음 소오스/드레인의 N+이온을 주입하는 공정으로 구성된 것을 특징으로 하는 MOS트랜지스터.Forming a gate pattern by sequentially forming a gate oxide, a first gate polysilicon, a first oxide, a second gate polysilicon, and a second oxide on a silicon substrate; and a second oxide, a second gate polysilicon, and a first oxide. Etching only the source / drain portions of and forming N - regions by implanting M - ions, forming polysilicon for sidewalls, and etching polysilicon and first gate polysilicon for sidewalls. Forming a polysilicon sidewall electrically connecting the polysilicon and the second gate polysilicon; forming an oxide for the sidewall; and etching the oxide and gate oxide into the sidewall to separate the gate and the source / drain. Form oxide sidewalls to reduce overlap, then N + ions of the source / drain MOS transistor, characterized in that consisting of a process for injecting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000557A 1991-01-15 1991-01-15 Manufacturing method for mos-tr KR940002777B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000557A KR940002777B1 (en) 1991-01-15 1991-01-15 Manufacturing method for mos-tr

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000557A KR940002777B1 (en) 1991-01-15 1991-01-15 Manufacturing method for mos-tr

Publications (2)

Publication Number Publication Date
KR920015437A true KR920015437A (en) 1992-08-26
KR940002777B1 KR940002777B1 (en) 1994-04-02

Family

ID=19309824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000557A KR940002777B1 (en) 1991-01-15 1991-01-15 Manufacturing method for mos-tr

Country Status (1)

Country Link
KR (1) KR940002777B1 (en)

Also Published As

Publication number Publication date
KR940002777B1 (en) 1994-04-02

Similar Documents

Publication Publication Date Title
KR910020842A (en) LDD type CMOS device manufacturing method
KR910001993A (en) Manufacturing Method of Semiconductor Device
KR920022562A (en) Semiconductor Integrated Circuit Manufacturing Method
KR920015437A (en) MOS transistor
KR920020594A (en) LDD transistor structure and manufacturing method
KR960026459A (en) Transistor Manufacturing Method
KR920015592A (en) LDD structure transistor manufacturing method
KR970054387A (en) Most transistor manufacturing method
KR900004035A (en) Manufacturing method of morph transistors having different operating ranges
KR950012645A (en) Method of manufacturing thin film transistor of semiconductor device
KR910020934A (en) TITA Morse FET Manufacturing Method and Structure
KR950026008A (en) Gate electrode shared transistor
KR880013258A (en) Manufacturing Method of Semiconductor Device
EP0309828A3 (en) An electronic semiconductor device, in particular a silicon-gate field-effect mos transistor, for high input voltages
KR930001476A (en) Transistor manufacturing method
KR980005881A (en) Method of manufacturing semiconductor device
KR910019204A (en) LDD manufacturing method using slop gate
KR920013601A (en) MOS transistor manufacturing method
KR920005363A (en) Manufacturing Method and Structure of MOS Transistor
KR920013755A (en) Morse transistor using multi-gate and manufacturing method thereof
KR920008963A (en) Channel Doping Method of MOS Transistor
KR890002992A (en) Manufacturing method of MOS field effect transistor
KR960035917A (en) Semiconductor device manufacturing method
KR950004565A (en) Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof
KR920013767A (en) Method of manufacturing a hot carrier prevention transistor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050322

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee