KR940007988A - Structure of Contact Window of Semiconductor Device and Formation Method - Google Patents

Structure of Contact Window of Semiconductor Device and Formation Method Download PDF

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KR940007988A
KR940007988A KR1019920016825A KR920016825A KR940007988A KR 940007988 A KR940007988 A KR 940007988A KR 1019920016825 A KR1019920016825 A KR 1019920016825A KR 920016825 A KR920016825 A KR 920016825A KR 940007988 A KR940007988 A KR 940007988A
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forming
trench
spacer
contact window
semiconductor substrate
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KR960000370B1 (en
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이주영
이규필
박용직
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 특히 소정의 물질층에 형성된 트랜치, 상기 트랜치의 표면에 형성된 절연층 및 상기 절연층에 형성되고 상기 소정의 물질층의 표면으로 부터 소정의 깊이에 형성되며 그 가장자리가 서로 연결되는 형태로 형성되어 상기 트렌치의 표면을 부분적으로 노출시키는 접촉창을 포함하는 접촉창의 구조 및 그 형성방법을 제공한다. 따라서, 수직구조로 형성된 접촉창에서 도전물질 간의 접촉을 신뢰성 있게 달성할수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a trench formed in a predetermined material layer, an insulating layer formed on a surface of the trench, and a predetermined depth formed from the surface of the insulating material layer. And a contact window formed in a shape in which edges thereof are connected to each other to partially expose the surface of the trench, and a method of forming the contact window. Therefore, contact between the conductive materials can be reliably achieved in the contact window formed in the vertical structure.

Description

반도체장치의 접촉창의 구조 및 그 형성방법Structure of Contact Window of Semiconductor Device and Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 방법에 의해 제조된 반도체 메모리장치의 주요부를 도시한 단면도.4 is a cross-sectional view showing a main portion of a semiconductor memory device manufactured by the method of the present invention.

Claims (18)

소정의 물질층에 형성된 트렌치, 상기 트렌치의 표면에 형성된 절연층, 및 상기 절연층에 형성되고 상기 소정의 물질층의 표면으로부터 소정의 깊이에 형성되며 그 가장자리가 서로 연결되는 형태로 형성되어 상기 트랜치의 표면을 부분적으로 노출시키는 접촉창을 포함하는 반도체장치의 접촉창의 구조.A trench formed in a predetermined material layer, an insulating layer formed on a surface of the trench, and a trench formed in the insulating layer and formed at a predetermined depth from a surface of the predetermined material layer and having edges connected to each other. A contact window structure of a semiconductor device comprising a contact window that partially exposes a surface of the semiconductor device. 제1항에 있어서, 상기 소정깊이는 소정의 물질층에 형성되는 도전영역의 두께 이하인 것을 특징으로 하는 반도체장치의 접촉창의 구조.The contact window structure of claim 1, wherein the predetermined depth is equal to or less than a thickness of a conductive region formed in a predetermined material layer. 제1항 또는 제2항에 있어서, 상기 소정의 물질층은 반도체기판인 것을 특징으로 하는 반도체장치의 접촉창의 구조.The structure of a contact window of a semiconductor device according to claim 1 or 2, wherein said predetermined material layer is a semiconductor substrate. 제3항에 있어서, 상기 접촉차에 의해 노출된 트렌치의 표면과 메모리장치의 커패시터의 일부가 연결되는 구조로 형성된 것을 특징으로 하는 반도체장치의 접촉창의 구조.4. The structure of a contact window of claim 3, wherein a surface of the trench exposed by the contact difference and a portion of a capacitor of the memory device are connected to each other. 제4항에 있어서, 상기 도전영역은 트랜지스터의 소오스 영역이고 상기 커패시터의 일부는 스토리지전극의 일부인 것을 특징으로 하는 반도체장치의 접촉창의 구조.The structure of a contact window of claim 4, wherein the conductive region is a source region of a transistor and a portion of the capacitor is part of a storage electrode. 소정의 물질층에 제1의 트랜치를 형성하는 공정, 상기 제1의 트랜치 표면에 제1의 스페이서를 식각대상물질로 한 이방성식각을 행하여 제2의 스페이서를 형성하는 공정, 도전영역이 형성될 영역의 소정의 물질층과 접하는 제1의 스페이서만 남기는 공정, 제1의 트렌치 내에 상기 제1의 스페이서를 형성하는 공정, 제2의 스페이서가 형성된 영역을 제외한 트랜치 표면에 절연층을 형성하는 공정, 및 상기 제2의 스페이서를 제거하는 공정을 포함하는 반도체장치의 접촉창 형성방법.Forming a first trench in a predetermined material layer, performing anisotropic etching using a first spacer as an etching target material on the surface of the first trench to form a second spacer, and a region in which a conductive region is to be formed Leaving only a first spacer in contact with a predetermined layer of material, forming the first spacer in a first trench, forming an insulating layer on the trench surface except the region where the second spacer is formed, and And removing the second spacer. 제6항에 있어서, 상기 소정의 물질층으로 반도체기판을 사용하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.7. The method of claim 6, wherein a semiconductor substrate is used as the predetermined material layer. 제7항에 있어서, 상기 도전영역은 트랜지스터의 소오스 영역인 것을 특징으로 하는 반도체장치의 접촉창 형성방법.8. The method of claim 7, wherein the conductive region is a source region of a transistor. 제7항에 있어서, 제1의 트렌치를 형성하는 상기 공정은, 필드산화막이 형성되어 있는 반도체기판 전면에 제1산화막을 형성하는 공정, 상기 제1산화막 전면에 제1질화물층을 형성하는 공정, 상기 제1질화물층 전면에 제2산화막을 형성하는 공정, 제1의 트렌치가 형성될 영역의 반도체기판이 노출되도록 상기 제1산화막, 제1질화물층 및 제2산화막을 제거하는 공정, 및 노출된 상기 반도체기판을 소정의 깊이로 식각하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 7, wherein the forming of the first trench comprises: forming a first oxide film on the entire surface of the semiconductor substrate on which the field oxide film is formed; forming a first nitride layer on the entire surface of the first oxide film; Forming a second oxide film over the entire surface of the first nitride layer, removing the first oxide film, the first nitride layer, and the second oxide film to expose the semiconductor substrate in the region where the first trench is to be formed, and Forming a contact window of the semiconductor device, wherein the semiconductor substrate is etched to a predetermined depth. 제6항 또는 제9항에 있어서, 상기 제1의 스페이서를 구성하는 물질로 향산화물질을 사용하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of forming a contact window of a semiconductor device according to claim 6 or 9, wherein a fragrant oxide is used as a material forming the first spacer. 제10항에 있어서, 상기 항산화물질로 실리콘질화물을 사용하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 10, wherein silicon nitride is used as the antioxidant. 제6항 또는 제8항에 있어서, 제1의 트랜치 내에 상기 제1의 스페이서를 식각대상물로 한 이방성식각을 행하여 제2의 스페이서를 형성하는 상기 공정시, 제1의 트렌치를 통해 표면으로 노출된 반도체기판도 소정깊이로 재식각하여 제2의 트렌치를 형성하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 6 or 8, wherein during the process of performing anisotropic etching using the first spacer as an etch target in the first trench to form a second spacer, the surface is exposed to the surface through the first trench. And forming a second trench by reetching the semiconductor substrate to a predetermined depth. 제9항에 있어서, 제1의 스페이서를 형성하는 상기 공정은 노출된 반도체기판을 소정 깊이로 식각하는 상기 공정 이후에, 결과를 전면에 제2질화물층을 형성하는 공정, 및 제2질화물층을 식각대상물로 한 이방성식각을 결과물 전면에 행하는 공정으로 진행되는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 9, wherein the forming of the first spacer comprises: forming a second nitride layer on the entire surface after the etching of the exposed semiconductor substrate to a predetermined depth; A method of forming a contact window in a semiconductor device, characterized in that the step of performing anisotropic etching as an etching target on the entire surface of the resultant product. 제13항에 있어서, 도전영역이 형성될 영역의 소정의 물질층과 접하는 제1의 스페이서만 남기는 공정은, 제2질화물층을 식각대상물로 한 이방성식각을 결과물 전면에 행하는 공정 이후에, 전면에 제3산화막을 형성하는 공정, 제1의 트렌치를 완전히 채우고 제3산화막 상에서는 일정한 두께를 갖는 형태로 포토레지스트를 도포하는 공정, 도전영역이 형성될 영역에만 포토레지스트가 남도록 상기 포토레지스트를 노광 및 현상하여 포토레지스트 패턴을 형성하는 공정, 표면으로 노출된 제3산화막을 제거하는 공정, 포토레지스트 패턴을 제거하는 공정, 및 남은 제3산호막을 식각마스크로 하여 표면으로 노출된 제2질화막층을 제거하는 공정으로 진행되는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The process of claim 13, wherein the step of leaving only the first spacers in contact with the predetermined material layer of the region where the conductive region is to be formed is performed after the step of performing anisotropic etching on the entire surface of the resultant with the second nitride layer as an etch target. Forming a third oxide film, completely filling the first trenches, and applying a photoresist in a form having a constant thickness on the third oxide film; exposing and developing the photoresist such that the photoresist remains only in a region where a conductive region is to be formed; Forming a photoresist pattern, removing a third oxide film exposed to the surface, removing a photoresist pattern, and removing the second nitride film layer exposed to the surface using the remaining third coral film as an etching mask. A contact window forming method of a semiconductor device, characterized in that the process proceeds. 제12항에 있어서, 반도체기판을 소정깊이로 재식각하는 상기 식각공정에 사용되는 식각조건은 반도체기판＞질화물층＞산화막 순으로 식각율이 정해지도록 조절되는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 12, wherein the etching conditions used in the etching process for re-etching the semiconductor substrate to a predetermined depth is controlled so that the etching rate is determined in the order of semiconductor substrate> nitride layer> oxide film. Way. 제6항에 있어서, 제2의 스페이서는 그 최상부 표면이 소정의 물질층 표면을 그 기준으로 했을때 약 2,000Å정도의 깊이에 위치되도록 형성되는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.7. The method according to claim 6, wherein the second spacer is formed such that its uppermost surface is located at a depth of about 2,000 mm based on the surface of a predetermined material layer as a reference. 제8항에 있어서, 상기 제2의 스페이서를 제거하는 공정이후, 결과물 전면에 도전물질을 증착한후 이방성식각하여 스토리지전극을 형성하는 공정을 추가하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.The method of claim 8, further comprising, after removing the second spacer, depositing a conductive material on the entire surface of the resultant and then anisotropically etching the storage electrode to form a storage electrode. 제17항에 있어서, 결과물 전면에 도전물질을 증착한후 이방성성식각하여 스토리전극을 형성하는 상기 공정에 있어서 상기 이방성식각 공정은 트랜치가 형성된 반도체기판을 제외한 반도체기판 상에 상기 스토리지전극을 구성하는 도전물질이 남지 않을때 까지 진행되는 것을 특징으로 하는 반도체장치의 접촉창 형성방법.18. The method of claim 17, wherein in the step of forming a story electrode by anisotropic etching after depositing a conductive material on the entire surface of the resultant, the anisotropic etching process comprises forming the storage electrode on a semiconductor substrate except for the trench-formed semiconductor substrate. The method of forming a contact window in a semiconductor device, characterized in that it proceeds until no conductive material remains. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920016825A 1992-09-16 1992-09-16 Contact hole structure and forming method thereof KR960000370B1 (en)

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