KR970052224A - Method for forming contact field of semiconductor device - Google Patents

Method for forming contact field of semiconductor device Download PDF

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Publication number
KR970052224A
KR970052224A KR1019950049699A KR19950049699A KR970052224A KR 970052224 A KR970052224 A KR 970052224A KR 1019950049699 A KR1019950049699 A KR 1019950049699A KR 19950049699 A KR19950049699 A KR 19950049699A KR 970052224 A KR970052224 A KR 970052224A
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KR
South Korea
Prior art keywords
material layer
forming
spacer
insulating layer
etching
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Application number
KR1019950049699A
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Korean (ko)
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KR0165354B1 (en
Inventor
서영우
신윤승
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김광호
삼성전자 주식회사
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Priority to KR1019950049699A priority Critical patent/KR0165354B1/en
Publication of KR970052224A publication Critical patent/KR970052224A/en
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Publication of KR0165354B1 publication Critical patent/KR0165354B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 장치의 접촉창 형성방법에 대해 기재되어 있다. 반도체 기판상에 형성된 절연층 상에 상기 절연층의 소정영역 노출시키는 개구부를 갖는 제1물질층 패턴을 형성하는 단계, 상기 개구부의 측벽에 제2물질층으로 이루어진 스페이서를 형성하는 단계, 상기 제1물질층 패턴 및 상기 스페이서를 마스크로 하여 상기 절연층을 일정깊이만큼 식각하는 단계, 상기 제1물질층 패턴 및 상기 스페이서를 제거하는 단계, 상기 일정깊이만큼 식각된 부분 아래의 반도체 기판이 노출될때까지 상기 절연층을 전면 식각하여 접촉창을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 접촉창 형성방법에 의하면, 접촉창에 언더컷이 형성되지 않으므로 플러그 또는 도전층 형성시 보이드가 발생하는 현상을 제거할 수 있다.A method for forming a contact window of a semiconductor device is described. Forming a first material layer pattern having an opening exposing a predetermined region of the insulating layer on an insulating layer formed on a semiconductor substrate, forming a spacer formed of a second material layer on a sidewall of the opening; Etching the insulating layer to a predetermined depth using the material layer pattern and the spacer as a mask, removing the first material layer pattern and the spacer, until the semiconductor substrate under the portion etched to the predetermined depth is exposed. According to a method of forming a contact window of a semiconductor device, the method may further include forming a contact window by etching the entire insulating layer. Can be removed.

Description

반도체 장치의 접촉창 형성방법Method of forming contact window of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도 내지 2e도는 본 발명의 제1실시예에 의한 반도체 장치의 접촉창 형성방법을 설명하기 위한 단면도들이다.2A to 2E are cross-sectional views illustrating a method of forming a contact window of a semiconductor device according to a first embodiment of the present invention.

Claims (6)

반도체 기판상에 형성된 절연층 상에 상기 절연층의 소정영역을 노출시키는 개구부를 잦는 제1물질층 패턴을 형성하는 단계; 상기 개구부의 측벽에 제2물질층으로 이루어진 스페이서를 형성하는 단계; 상기 제1물질층 패턴 및 상기 스페이서를 마스크로 하여 상기 절연층을 일정깊이만큼 식각하는 단계; 상기 제1물질층 패턴 및 상기 스페이서를 제거하는 단계; 상기 일정깊이만큼 식각된 부분 아래의 반도체 기판이 노출될때까지 상기 절연층을 전면 식각하여 접촉창을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.Forming a first material layer pattern on the insulating layer formed on the semiconductor substrate, the first material layer pattern having an opening exposing a predetermined region of the insulating layer; Forming a spacer including a second material layer on sidewalls of the opening; Etching the insulating layer by a predetermined depth using the first material layer pattern and the spacer as a mask; Removing the first material layer pattern and the spacer; Forming a contact window by etching the entire surface of the insulating layer until the semiconductor substrate under the portion etched by the predetermined depth is exposed. 제1항에 있어서, 상기 제1물질층 패턴은 폴리실리콘으로 이루어진 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.The method of claim 1, wherein the first material layer pattern is made of polysilicon. 제1항에 있어서, 상기 스페이서는 폴리실리콘으로 이루어진 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.The method of claim 1, wherein the spacer is made of polysilicon. 반도체 기판상에 차례로 적층된 절연층 및 제1물질층 상에 상기 제1물질층의 소정영역을 노출시키는 개구부를 갖는 감광막 패턴을 형성하는 단계; 상기 개구부의 측벽에 제2물질층으로 이루어진 스페이서를 형성하는 단계; 상기 감광막 패턴 및 상기 스페이서를 마스크로 하여 상기 노출된 제1물질층을 식각하여 그 아래의 절연층을 노출시키는 단계 및 상기 노출된 절연층을 일정깊이만큼 식각하는 단계; 상기 감광막 패턴, 상기 스페이서 및 상기 제1물질층을 제거하는 단계; 상기 일정깊이 만큼 식각된 부분 아래의 반도체 기판이 노출될때까지 상기 절연층을 전면 식각하여 접촉창을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.Forming a photoresist pattern having an insulating layer sequentially stacked on a semiconductor substrate and an opening exposing a predetermined region of the first material layer on the first material layer; Forming a spacer including a second material layer on sidewalls of the opening; Etching the exposed first material layer by using the photoresist pattern and the spacer as a mask to expose an insulating layer below it, and etching the exposed insulating layer to a predetermined depth; Removing the photoresist pattern, the spacer and the first material layer; And forming a contact window by etching the entire surface of the insulating layer until the semiconductor substrate under the portion etched by the predetermined depth is exposed. 제4항에 있어서, 상기 제1물질층은 폴리실리콘으로 이루어진 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.The method of claim 4, wherein the first material layer is made of polysilicon. 제4항에 있어서, 상기 스페이서는 폴리머로 이루어진 것을 특징으로 하는 반도체 장치의 접촉창 형성방법.The method of claim 4, wherein the spacer is made of a polymer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950049699A 1995-12-14 1995-12-14 Method of forming a contact hole of semiconductor device KR0165354B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950049699A KR0165354B1 (en) 1995-12-14 1995-12-14 Method of forming a contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950049699A KR0165354B1 (en) 1995-12-14 1995-12-14 Method of forming a contact hole of semiconductor device

Publications (2)

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KR970052224A true KR970052224A (en) 1997-07-29
KR0165354B1 KR0165354B1 (en) 1999-02-01

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