KR0146629B1 - Method for forming field oxide film of semiconductor device - Google Patents
Method for forming field oxide film of semiconductor deviceInfo
- Publication number
- KR0146629B1 KR0146629B1 KR1019940038574A KR19940038574A KR0146629B1 KR 0146629 B1 KR0146629 B1 KR 0146629B1 KR 1019940038574 A KR1019940038574 A KR 1019940038574A KR 19940038574 A KR19940038574 A KR 19940038574A KR 0146629 B1 KR0146629 B1 KR 0146629B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- oxide film
- silicon
- film
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Weting (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 필드산화막의 균일한 형성을 위하여 실리콘질화막 상부에 비정질실리콘층을 소정의 두께로 형성하고 필드영역을 확정한 후 상기 실리콘질화막을 식각정지층으로 이용하여 상기 비정질실리콘층의 식각과 동시에 실리콘기판의 필드영역이 리세스구조가 되도록 식각하므로써 정확한 식각깊이의 구현으로 균일한 필드산화막을 형성할 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.The present invention relates to a method for forming a field oxide film of a semiconductor device, wherein an amorphous silicon layer is formed on a silicon nitride film to a predetermined thickness and a field region is determined to form a field oxide film uniformly, and then the silicon nitride film is used as an etch stop layer. By using the etching of the amorphous silicon layer and at the same time the field region of the silicon substrate to form a recess structure by using a method for forming a field oxide film of a semiconductor device capable of forming a uniform field oxide film with the implementation of the accurate etching depth.
Description
제1a 내지 제1h도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.1A to 1H are cross-sectional views of a device for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 패드 산화막1 silicon substrate 2 pad oxide film
3 : 실리콘질화막 4 : 비정질실리콘층3: silicon nitride film 4: amorphous silicon layer
5 : 감광막 6 : 질화막5: photosensitive film 6: nitride film
6A : 질화막스페이서 7 : 필드산화막6A: nitride film spacer 7: field oxide film
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 특히 실리콘질화막 상부에 비정질실리콘(Amorphous-Si)층을 소정의 두께로 형성하고 필드영역을 확정(Define)한 후 상기 실리콘질화막을 식각정지층으로 이용하여 상기 비정질실리콘층의 식각과 동시에 실리콘기판의 필드영역이 리세스(Recess)구조가 되도록 식각하므로써 정확한 식각깊이의 구현으로 균일한 필드산화막을 형성할 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a field oxide film of a semiconductor device. In particular, an amorphous silicon (Amorphous-Si) layer is formed on a silicon nitride film to a predetermined thickness and the field region is defined, and then the silicon nitride film is etched stop layer. A method of forming a field oxide film of a semiconductor device in which a uniform field oxide film is formed by realizing an accurate etching depth by etching the amorphous silicon layer so that the field region of a silicon substrate is a recess structure at the same time. It is about.
일반적으로 반도체 소자의 제조공정에서 소자와 소자사이를 분리시키기 위하여 소자분리막인 필드산화막을 형성시킨다.In general, a field oxide film, which is a device isolation film, is formed to separate devices from devices in a semiconductor device manufacturing process.
종래 반도체 소자의 필드산화막은 LOCOS(Local Oxidation of Silicon) 기술을 이용하여 형성하는데, 소자의 집적도가 증가됨에 따라 버즈빅(Bird's beak)길이의 증가로 인해 활성영역의 크기를 감소시키게 된다. 그러므로 큰 체적비(Volume ratio)와 작은 버즈빅길이를 실현하기 위하여 실리콘기판을 리세스구조로 식각하고 그 식각된 부분의 양측벽에 실링(Sealing)역할을 하도록 질화막을 형성하여 산화공정시 산화제의 측면확산을 억제하였다. 그러나 이와 같은 종래의 방법은 실리콘기판식각시 식각정지층(Etch stop layer)이 없기 때문에 단지 실리콘의 식각비(Etch rate)만을 이용한다. 이 방법은 실리콘기판의 식각깊이를 시간에 의해 조정하기 때문에 식각비에 따라 식각깊이가 민감하게 변화되고 또한, 사용가스량의 변화에도 민감하다. 그렇기 때문에 실리콘기판을 균일한 깊이롤 식각하기가 어렵고 이에 따라 필드산화막의 균일한 형성이 어려운 실정이다.The field oxide layer of a conventional semiconductor device is formed by using a local oxide of silicon (LOCOS) technology. As the integration degree of the device increases, the size of the active region decreases due to an increase in the length of the bird's beak. Therefore, in order to realize a large volume ratio and a small buzz big length, the silicon substrate is etched into a recess structure, and a nitride film is formed to act as a sealing on both side walls of the etched portion. Diffusion was suppressed. However, this conventional method uses only the etch rate of silicon because there is no etch stop layer during silicon substrate etching. In this method, since the etching depth of the silicon substrate is adjusted by time, the etching depth is sensitively changed depending on the etching ratio and is also sensitive to the change in the amount of gas used. Therefore, it is difficult to etch the silicon substrate uniformly in a roll, and thus, it is difficult to uniformly form the field oxide film.
따라서 본 발명은 실리콘질화막 상부에 비정질실리콘을 소정의 두께로 형성하고 필드영역을 확정한 후 상기 실리콘질화막을 식각정지층으로 이용하여 상기 비정질실리콘의 식각과 동시에 실리콘기판의 필드영역이 리세스구조가 되도록 식각하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 필드산화막 형성방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, after the amorphous silicon is formed on the silicon nitride film to a predetermined thickness and the field region is determined, the silicon nitride film is used as the etch stop layer, and the field region of the silicon substrate has a recess structure at the same time as the etching of the amorphous silicon. It is an object of the present invention to provide a method for forming a field oxide film of a semiconductor device which can solve the above disadvantages by etching.
상기한 목적을 달성하기 위한 본 발명은 패드산화막이 형성된 실리콘기판상에 실리콘질화막 및 비정질실리콘층을 순차적으로 형성시키는 단계와, 상기 단계로부터 전체면에 감광막을 도포한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝한 다음 패터닝된 상기 감광막을 마스크로 이용하여 필드영역의 비정질실리콘층, 실리콘질화막 및 패드산화막을 순차적으로 식각하는 단계와, 상기 단계로 부터 상기 감광막을 제거한 후 상기 비정질실리콘층과 노출된 실리콘기판을 식각하여 상기 실리콘기판을 리세스구조로 형성시키는 단계와, 상기 단계로부터 전체면에 질화막을 형성한 후 스페이서식각하여 상기 실리콘질화막, 패드산화막 및 실리콘기판의 식각된 측벽에 질화막스페이서를 형성시키는 단계와, 상기 단계로 부터 산화공정을 실시하여 필드영역에 필드산화막을 형성시키는 단계와, 상기 단계로 부터 상기 실리콘질화막과 질화막스페이서 그리고 패드산화막을 순차적으로 제거시키는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming a silicon nitride film and an amorphous silicon layer on the silicon substrate on which the pad oxide film is formed, and after applying the photosensitive film to the entire surface from the step using the device isolation mask Patterning the photoresist layer and subsequently etching the amorphous silicon layer, the silicon nitride layer, and the pad oxide layer in the field region using the patterned photoresist as a mask; Etching the silicon substrate to form the silicon substrate as a recess structure; forming a nitride film on the entire surface from the step; and etching the spacer to form a nitride film spacer on the etched sidewalls of the silicon nitride film, the pad oxide film, and the silicon substrate. And the oxidation process from the above step And forming a field oxide film in the field region, and sequentially removing the silicon nitride film, the nitride film spacer, and the pad oxide film from the step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1a 내지 제1h도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도로서,1A to 1H are cross-sectional views of devices for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
제1a도는 패드산화막(2)이 형성된 실리콘기판(1)상에 실리콘질화막(3) 및 비정질실리콘층(4)을 순차적으로 형성시킨 상태의 단면도인데, 이때 상기 비정질실리콘층(4)의 두께는 실리콘기판이 리세스구조로 식각되는 깊이와 동일하게 예를들어 300 내지 3000Å 정도로 형성한다.FIG. 1A is a cross-sectional view of a silicon nitride film 3 and an amorphous silicon layer 4 sequentially formed on a silicon substrate 1 on which a pad oxide film 2 is formed, wherein the thickness of the amorphous silicon layer 4 is The silicon substrate is formed to, for example, about 300 to 3000 microns in the same depth as that of the recess.
제1b도는 전체면에 감광막(5)을 도포한 후 소자분리마스크를 이용하여 상기 감광막(5)을 패터닝한 상태의 단면도이며, 제1c도는 패터닝된 상기 감광막(5)을 마스크로 이용하여 필드영역의 비정질실리콘층(4), 실리콘질화막(3) 및 패드산화막(2)을 순차적으로 건식식각한 상태의 단면도이다.FIG. 1B is a cross-sectional view of the photoresist layer 5 patterned using an element isolation mask after the photoresist layer 5 is applied to the entire surface, and FIG. 1C is a field region using the patterned photoresist layer 5 as a mask. Is a cross-sectional view of the amorphous silicon layer 4, the silicon nitride film 3, and the pad oxide film 2 in a dry dry state sequentially.
제1d도는 상기 감광막(5)을 제거한 후 상기 실리콘질화막(3)을 식각정지층으로 이용하여 상기 비정질실리콘(4)과 노출된 실리콘기판(1)을 식각한 상태의 단면도인데, 이때 일반적으로 비정질실리콘과 실리콘기판의 건식식각비는 1:1이므로 상기 비정질실리콘층(4)의 두께만큼의 실리콘기판(1)이 식각된다. 그러므로 이를 이용하여 상기 비정질실리콘층(4)의 두께를 조절하므로써 식각하고자 하는 실리콘기판의 깊이를 조절할 수 있다.FIG. 1D is a cross-sectional view of the amorphous silicon 4 and the exposed silicon substrate 1 being etched using the silicon nitride film 3 as an etch stop layer after removing the photoresist film 5. Since the dry etching ratio of silicon and the silicon substrate is 1: 1, the silicon substrate 1 as much as the thickness of the amorphous silicon layer 4 is etched. Therefore, it is possible to control the depth of the silicon substrate to be etched by adjusting the thickness of the amorphous silicon layer 4 using this.
제1e도는 전체면에 질화막(6)을 형성한 상태의 단면도이고, 제1f도는 상기 질화막(6)을 스페이서식각하여 상기 실리콘질화막(3), 패드산화막(2) 및 실리콘기판(1)의 식각된 측벽에 질화막스페이서(6A)를 형성시킨 상태의 단면도이다.FIG. 1E is a cross-sectional view of the nitride film 6 formed on the entire surface, and FIG. 1F is a spacer etched of the nitride film 6 to etch the silicon nitride film 3, the pad oxide film 2, and the silicon substrate 1. It is sectional drawing in the state which formed the nitride film spacer 6A in the formed side wall.
제1g도는 산화공정을 실시하여 필드영역에 필드산화막(7)을 형성시킨 상태의 단면도이고, 제1h도는 상기 실리콘질화막(3)과 질화막스페이서(6A)를 H3PO4용액을 이용하여 습식식각한 후 상기 패드산화막(2)을 제거하므로써 필드산화막(7)의 형성이 완료된 상태이다.FIG. 1g is a cross-sectional view of the field oxide film 7 being formed in the field region by performing an oxidation process, and FIG. 1h is a wet etching process of the silicon nitride film 3 and the nitride film spacer 6A using H 3 PO 4 solution. After the pad oxide film 2 is removed, the field oxide film 7 is formed.
상술한 바와 같이 본 발명에 의하면 실리콘질화막 상부에 비정질실리콘층을 소정의 두께로 형성하고 필드영역을 확정한 후 상기 실리콘질화막을 식각정지층으로 이용하여 상기 비정질실리콘층의 식각과 동시에 실리콘기판의 필드영역이 리세스구조가 되도록 식각하므로써 정확한 식각깊이의 구현으로 균일한 필드산화막을 형성할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the amorphous silicon layer is formed on the silicon nitride film to a predetermined thickness and the field region is determined, the silicon silicon film is used as an etch stop layer and the field of the silicon substrate is etched simultaneously with the etching of the amorphous silicon layer. By etching the region to be a recess structure, there is an excellent effect of forming a uniform field oxide film by implementing an accurate etching depth.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038574A KR0146629B1 (en) | 1994-12-29 | 1994-12-29 | Method for forming field oxide film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038574A KR0146629B1 (en) | 1994-12-29 | 1994-12-29 | Method for forming field oxide film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026578A KR960026578A (en) | 1996-07-22 |
| KR0146629B1 true KR0146629B1 (en) | 1998-11-02 |
Family
ID=19404791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940038574A KR0146629B1 (en) | 1994-12-29 | 1994-12-29 | Method for forming field oxide film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0146629B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733693B1 (en) * | 2001-12-29 | 2007-06-28 | 매그나칩 반도체 유한회사 | Method of forming a isolation layer in semiconductor device |
-
1994
- 1994-12-29 KR KR1019940038574A patent/KR0146629B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733693B1 (en) * | 2001-12-29 | 2007-06-28 | 매그나칩 반도체 유한회사 | Method of forming a isolation layer in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026578A (en) | 1996-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100187678B1 (en) | Method of forming an element isolation film in a semiconductor device | |
| KR0146629B1 (en) | Method for forming field oxide film of semiconductor device | |
| KR0122315B1 (en) | Micro-patterning method of semiconductor | |
| KR100186514B1 (en) | Isolation method of semiconductor device | |
| KR940009579B1 (en) | Manufacturing method of semiconductor device | |
| JPS63157444A (en) | Manufacture of selective oxide film | |
| KR100297098B1 (en) | Method for forming field oxide layer of semiconductor device | |
| KR100256269B1 (en) | Semiconductor element field oxidation layer manufacturing method | |
| KR19990003538A (en) | Manufacturing method of semiconductor device | |
| KR0168148B1 (en) | Method of forming field oxide film in a semiconductor device | |
| KR100253268B1 (en) | Semiconductor element isolation method | |
| JPS63258020A (en) | Formation of element isolation pattern | |
| KR100190036B1 (en) | Isolation method of semiconductor device | |
| KR0157921B1 (en) | Method of manufacturing field oxide film | |
| KR0125312B1 (en) | Field oxidation method of semiconductor device | |
| KR100226795B1 (en) | Method of forming a device isolation film of semiconductor device | |
| KR0166835B1 (en) | Method for forming isolation on a semiconductor device | |
| KR0131367B1 (en) | Method of forming field oxide film on the semiconductor device | |
| KR940003219B1 (en) | Element segregation method for semiconductor memory device | |
| KR19980030446A (en) | Semiconductor substrate and formation method thereof | |
| KR940003222B1 (en) | Prevention method for isolation birds beak by using mlr-structure | |
| KR100301251B1 (en) | Method for forming field oxide layer of semiconductor device | |
| KR100382547B1 (en) | method for forming capacitor semiconductor device | |
| KR100192439B1 (en) | Method for forming a contact hole of a semiconductor device | |
| KR100335776B1 (en) | Method for fabricating field oxide layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090427 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |