KR100256269B1 - Semiconductor element field oxidation layer manufacturing method - Google Patents

Semiconductor element field oxidation layer manufacturing method Download PDF

Info

Publication number
KR100256269B1
KR100256269B1 KR1019930028079A KR930028079A KR100256269B1 KR 100256269 B1 KR100256269 B1 KR 100256269B1 KR 1019930028079 A KR1019930028079 A KR 1019930028079A KR 930028079 A KR930028079 A KR 930028079A KR 100256269 B1 KR100256269 B1 KR 100256269B1
Authority
KR
South Korea
Prior art keywords
oxide film
film
oxide
field oxide
field
Prior art date
Application number
KR1019930028079A
Other languages
Korean (ko)
Other versions
KR950021357A (en
Inventor
강세억
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019930028079A priority Critical patent/KR100256269B1/en
Publication of KR950021357A publication Critical patent/KR950021357A/en
Application granted granted Critical
Publication of KR100256269B1 publication Critical patent/KR100256269B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE: A method of forming a field oxide is to reduce a width of the field oxide, compared with that in a conventional PBL(Poly Buffered LOCOS) process, thereby securing wider active region. CONSTITUTION: A pad oxide(2), a polysilicon layer(3), a nitride layer(4) and a CVD oxide is deposited on a semiconductor substrate(1) in this order and a photoresist pattern is formed thereon to define a field region. The CVD oxide and the nitride layer is etched obliquely so that a lower part of the etched portion becomes narrow, to expose a predetermined portion of the polysilicon layer. The photoresist pattern is removed and then the CVD oxide is removed by a wet-etching process. After a field oxide(7) is formed using an oxidation process, the polysilicon layer and the pad oxide are etched off.

Description

반도체 소자의 필드산화막 형성 방법Field oxide film formation method of a semiconductor device

제1도는 본 발명의 원리를 설명하기 위한 예시도.1 is an exemplary diagram for explaining the principle of the present invention.

제2a도 내지 제2e도는 본 발명에 따른 필드산화막 형성 공정을 나타내는 단면도.2A to 2E are sectional views showing a field oxide film forming process according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 반도체기판 2 : 패드산화막1 semiconductor substrate 2 pad oxide film

3 : 폴리실리콘막 4 : 질화막3: polysilicon film 4: nitride film

5 : CVD 산화막 6 : 감광막 마스크5: CVD oxide film 6: photosensitive film mask

7 : 필드산화막7: field oxide film

본 발명은 반도체 제조 공정중 소자를 개별적으로 분리시키는 필드산화막 형성 방법에 관한 것으로, 특히 서브 마이크론(Submicron) 이하의 소자에 적용되는 반도체 소자의 필드산화막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field oxide film formation method for separating devices individually during a semiconductor manufacturing process, and more particularly to a method for forming field oxide films for semiconductor devices applied to devices of submicron or less.

종래의 LOCOS(Local Oxidation of Silicon)기술에 의한 소자 분리는 버즈비크(bird's beak)가 길게 형성되어 서브마이크론 반도체 공정에서는 한계가 있어, 새로운 소자 분리 기술이 적용되고 있으며 그 중의 한가지가 PBL(Poly Buffered LOCOS)기술이다. 그러나, PBL 기술에서도 버즈비크 문제(LOCOS 보다는 짧지만)가 여전히 남아 있어서 활성영역 확보가 여전히 힘들다.Device isolation by conventional LOCOS (Local Oxidation of Silicon) technology has a long bird's beak and is limited in the submicron semiconductor process, and a new device isolation technology is applied, and one of them is PBL (Poly Buffered). LOCOS) technology. However, in the PBL technology, the Buzzbeek problem (although shorter than LOCOS) still remains, so securing the active area is still difficult.

따라서, 본 발명은 PBL 공정을 수행함에 있어 CVD 산화막을 이용하여 식각 바이어스를 유도하므로써 이후에 형성되는 필드산화막의 폭을 좁히고 활성영역을 많이 확보하는 반도체 소자의 필드산화막 형성 방법을 제공하는데 그 목적으로 한다.Accordingly, the present invention provides a method for forming a field oxide film of a semiconductor device in which the etching of the CVD oxide film is used to perform the PBL process, thereby narrowing the width of the field oxide film formed later and securing a large number of active regions. do.

상기 목적을 달성하기 위하여 본 발명은, 반도체 소자의 필드산화막 형성 방법에 있어서, 반도체기판에 패드산화막, 폴리실리콘막, 질화막, CVD 산화막을 차례로 증착하고 필드영역을 디파인(Define) 하기 위한 감광막 마스크를 형성하는 제1 단계, 식각부위의 하부가 점차 좁아지도록 상기 CVD 산화막과 상기 질화막을 경사지게 식각하여 상기 폴리실리콘막의 소정부위가 노출되게 하는 제2단계, 상기 감광막 마스크를 제거하는 제3단계, 산화공정에 의해 필드산화막을 형성하는 제4단계, 및 상기 필드산화막을 제외한 상기 반도체 실리콘기판상에 적층된 박막들을 제거하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a field oxide film of a semiconductor device, comprising: depositing a pad oxide film, a polysilicon film, a nitride film, and a CVD oxide film on a semiconductor substrate, and then defining a photoresist mask for defining a field region. The first step of forming, the second step to etch the CVD oxide film and the nitride film inclined so that the lower portion of the etching portion is gradually narrowed, to expose a predetermined portion of the polysilicon film, the third step of removing the photosensitive film mask, the oxidation process And a fifth step of forming a field oxide film, and a fifth step of removing thin films deposited on the semiconductor silicon substrate except for the field oxide film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

먼저, 제1도를 통해 본 발명의 원리를 설명하기로 한다.First, the principle of the present invention will be described with reference to FIG.

반도체 기판(1)상에 패드(pad) 산화막(2), 폴리실리콘막(3), 질화막(4), CVD 산화막(5)을 차례로 형성한 후, 포토리소그래피(Photolithography) 공정에 의해 감광막 마스크(6)를 형성한 다음에 상기 CVD 산화막(5)과 질화막(4)을 건식식각해서 폴리실리콘막(3)이 노출되도록 한 상태의 단면도이다.After the pad oxide film 2, the polysilicon film 3, the nitride film 4, and the CVD oxide film 5 are formed in this order on the semiconductor substrate 1, a photoresist mask is formed by a photolithography process. 6) is a cross-sectional view of the CVD oxide film 5 and the nitride film 4 by dry etching so that the polysilicon film 3 is exposed.

이때, 도면에 도시된 바와 같이 건식식각시 FI CD(Final Inspection Critical Dimension)는 일반적으로 DI CD(Develop Inspection Critical Dimension)보다 작게 되는데, 질화막 상부에 CVD 산화막을 첨가하면 이러한 현상은 더 심하게 발생한다. 따라서 본 발명에서는 이 현상을 이용하여 식각 바이어스(DI CD - FI CD)를 약 0.10μm 정도로 유발시켜 필드산화막이 형성된 부위를 좁게해서 소자분리 측면에서는 오히려 더 유리하게 하는 것이다. 즉, FI CD가 작으면 필드산화막의 폭도 그 만큼 줄어들어 넓은 활성영역(active region)의 확보가 가능하다.In this case, as shown in the drawing, the final inspection critical dimension (FI CD) is generally smaller than the development inspection critical dimension (DI CD) in dry etching, and this phenomenon occurs more seriously when CVD oxide is added on the nitride film. Therefore, in the present invention, this phenomenon is used to cause an etching bias (DI CD-FI CD) to about 0.10 μm to narrow the portion where the field oxide film is formed, which is more advantageous in terms of device isolation. In other words, if the FI CD is small, the width of the field oxide film is reduced by that much, thereby securing a large active region.

제2a도 내지 제2e도는 상기와 같은 원리를 이용한 본 발명에 따른 필드산화막 형성 공정도로서, 제2a도는 반도체기판(1)에 패드산화막(2)을 100~200Å 열적으로 성장한 후, 폴리실리콘막(3)을 300~600Å, 질화막(4)을 2000~3000Å, CVD 산화막(5)을 300~700Å으로 차례로 증착하고 필드영역을 디파인(Define) 하기 위한 감광막 마스크(6)를 형성한 상태의 단면도이다.2a to 2e is a process chart for forming a field oxide film according to the present invention using the above-described principle, Figure 2a is a polysilicon film (100-200Å thermally grown after the pad oxide film 2 on the semiconductor substrate 1) 3) A cross-sectional view of a state in which a photosensitive film mask 6 for forming a field region is formed by depositing 300 to 600 Hz, a nitride film 4 to 2000 to 3000 Hz, and a CVD oxide film 5 to 300 to 700 Hz. .

이어서, 제2b도에 도시된 바와 같이 건식 식각 방법으로 상기 CVD 산화막(5)과 질화막(4)을 식각하여 폴리실리콘막(3)이 노출되게 한다. (이때, CVD 산화막과 질화막의 식각 비율은 비슷하므로 동시에 한가지 식각 방법으로 식각된다.)Subsequently, as illustrated in FIG. 2B, the CVD oxide film 5 and the nitride film 4 are etched by a dry etching method so that the polysilicon film 3 is exposed. (At this time, the etching ratio of the CVD oxide film and the nitride film is similar, so it is etched by one etching method at the same time.)

계속해서, 제2c도와 같이 상기 감광막 마스크(6)를 제거한 후, 습식 방법으로 CVD 산화막(5)을 제거하고, 제2d도와 같이 필드산화막(7)을 형성한다.Subsequently, after removing the photosensitive film mask 6 as shown in FIG. 2C, the CVD oxide film 5 is removed by a wet method, and the field oxide film 7 is formed as shown in FIG. 2D.

이때, CVD 산화막(5)을 제거하지 않은 상태에서 필드산화막(7)을 형성할 수도 있다.At this time, the field oxide film 7 may be formed without removing the CVD oxide film 5.

끝으로, 제2e도와 같이 습식식각으로 질화막(4)을 제거하고, 건식 식각으로 폴리실리콘(3)을 제거한 후, 다시 습식으로 패드산화막(2)을 제거하면 최종적으로 필드산화막(7)만 남게 된다.Finally, as shown in FIG. 2e, when the nitride film 4 is removed by wet etching, the polysilicon 3 is removed by dry etching, and the pad oxide film 2 is removed by wet again, only the field oxide film 7 remains. do.

이상 상기에서 설명한 바와 같이 이루어지는 본 발명은 FI CD 이득을 약 0.10μm 확보한 상태에서 필드산화막을 형성하기 때문에, 종래의 PBL 공정보다 필드산화막의 폭을 약 0.10μm 줄여서 버즈비크가 활성영역으로 들어가는 정도를 줄여주어 넓은 활성영역을 확보하는 효과가 있다.As described above, in the present invention, since the field oxide film is formed while the FI CD gain is about 0.10 μm, the width of the field oxide film is reduced by about 0.10 μm compared with the conventional PBL process, and the extent to which the Buzzbeek enters the active region. Reduces the effect of securing a wide active area.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (2)

반도체 소자의 필드산화막 형성 방법에 있어서, 반도체기판에 패드산화막, 폴리실리콘막, 질화막, CVD 산화막을 차례로 증착하고 필드영역을 디파인(Define) 하기 위한 감광막 마스크를 형성하는 제1단계; 식각부위의 하부가 점차 좁아지도록 상기 CVD 산화막과 상기 질화막을 경사지게 식각하여, 상기 폴리실리콘막의 소정부위가 노출되게 하는 제2단계; 상기 감광막 마스크를 제거하는 제3단계; 산화공정에 의해 필드산화막을 형성하는 제4단계; 및 상기 필드산화막을 제외한 상기 반도체기판 상에 적층된 박막들을 제거하는 제5단계를 포함하여 이루어진 반도체 소자의 필드산화막 형성 방법.A method of forming a field oxide film of a semiconductor device, comprising: a first step of depositing a pad oxide film, a polysilicon film, a nitride film, and a CVD oxide film on a semiconductor substrate and forming a photoresist mask for defining a field region; A second step of etching the CVD oxide film and the nitride film inclinedly so that the lower portion of the etching portion becomes narrower so that a predetermined portion of the polysilicon film is exposed; Removing the photoresist mask; A fourth step of forming a field oxide film by an oxidation process; And a fifth step of removing the thin films stacked on the semiconductor substrate except for the field oxide film. 제1항에 있어서, 상기 CVD 산화막은 상기 제3단계 또는 상기 제5단계에서 제거하는 것을 특징으로 하는 반도체 소자의 필드산화막 형성 방법.The method of claim 1, wherein the CVD oxide film is removed in the third step or the fifth step.
KR1019930028079A 1993-12-16 1993-12-16 Semiconductor element field oxidation layer manufacturing method KR100256269B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930028079A KR100256269B1 (en) 1993-12-16 1993-12-16 Semiconductor element field oxidation layer manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930028079A KR100256269B1 (en) 1993-12-16 1993-12-16 Semiconductor element field oxidation layer manufacturing method

Publications (2)

Publication Number Publication Date
KR950021357A KR950021357A (en) 1995-07-26
KR100256269B1 true KR100256269B1 (en) 2000-05-15

Family

ID=19371299

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930028079A KR100256269B1 (en) 1993-12-16 1993-12-16 Semiconductor element field oxidation layer manufacturing method

Country Status (1)

Country Link
KR (1) KR100256269B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63253650A (en) * 1987-04-10 1988-10-20 Toshiba Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63253650A (en) * 1987-04-10 1988-10-20 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
KR950021357A (en) 1995-07-26

Similar Documents

Publication Publication Date Title
US5397732A (en) PBLOCOS with sandwiched thin silicon nitride layer
US6867143B1 (en) Method for etching a semiconductor substrate using germanium hard mask
US5135884A (en) Method of producing isoplanar isolated active regions
KR100256269B1 (en) Semiconductor element field oxidation layer manufacturing method
KR20000042870A (en) Forming method of trench of semiconductor device
KR0141106B1 (en) Semiconductor device and making method thereof
KR0146629B1 (en) Method for forming field oxide film of semiconductor device
KR19990003538A (en) Manufacturing method of semiconductor device
KR100297098B1 (en) Method for forming field oxide layer of semiconductor device
KR960014450B1 (en) Method of isolation of a semiconductor device
KR19980084300A (en) Device isolation film formation method using a reflection suppression film
KR0168148B1 (en) Method of forming field oxide film in a semiconductor device
KR100190371B1 (en) Method of forming an element isolation oxide film in a semiconductor device
KR100196422B1 (en) Method for forming an element isolation region in a semiconductor device
KR100528797B1 (en) Method of forming an isolation film in a semiconductor device
KR100353819B1 (en) Method for manufacturing semiconductor device
KR100422960B1 (en) Method for forming isolation layer of semiconductor device
KR0148611B1 (en) Formation method of element isolation layer for semiconductor devices
KR0146526B1 (en) Method of forming insulating film for semiconductor device
KR100192439B1 (en) Method for forming a contact hole of a semiconductor device
KR100195192B1 (en) Pad poly forming method of semiconductor device
KR100249167B1 (en) Isolating film manufacturing method
KR940003222B1 (en) Prevention method for isolation birds beak by using mlr-structure
JP2992171B2 (en) Method for manufacturing semiconductor device
KR100335776B1 (en) Method for fabricating field oxide layer of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061211

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee