JPS63253650A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63253650A JPS63253650A JP8697687A JP8697687A JPS63253650A JP S63253650 A JPS63253650 A JP S63253650A JP 8697687 A JP8697687 A JP 8697687A JP 8697687 A JP8697687 A JP 8697687A JP S63253650 A JPS63253650 A JP S63253650A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- oxide film
- etched
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 64
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 4
- 230000000873 masking effect Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 2
- 210000003323 beak Anatomy 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 241000293849 Cordylanthus Species 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000004043 dyeing Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、半導体装置の製造方法に関し、特に隣接素子
間を絶縁分離する技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for insulating and separating adjacent elements.
（従来の技術）
現在、選択酸化法（ ＬＯＣＯＳ法）を用いた素子分離
技術が広く用いられているがバーズピーク（鳥の口ばし
）と呼はれる酸化膜の領域が素子領域に入シ込むため、
サブミクロンの素子分離領域を形成するには、この方法
は適していない。(Prior art) At present, element isolation technology using selective oxidation (LOCOS) is widely used, but a region of the oxide film called a bird's beak enters the element region. In order to include
This method is not suitable for forming submicron isolation regions.
（発明が解決しようとする問題点）
不発明はバーズビークを最小限に押え、しかも酸化時の
ストレスにより生ずる結晶欠陥をなくした素子分離を１
する半導体装置の製造方法を提供することを目的とする
。(Problems to be solved by the invention) The invention is to minimize the bird's beak and to eliminate crystal defects caused by stress during oxidation.
An object of the present invention is to provide a method for manufacturing a semiconductor device.
（問題点を解決するための手段）
本発明において、素子分離酸化膜を形成する前に素子領
域に残されたマスク材に角度をもたせ、またこのマスク
材の外側にフレーム状の耐酸化薄膜を形成する。(Means for Solving the Problems) In the present invention, before forming the element isolation oxide film, the mask material left in the element region is made to have an angle, and a frame-shaped oxidation-resistant thin film is formed on the outside of this mask material. Form.
（作用）
本発明において素子領域に残されたマスク材に角度をも
たせかつこのマスク材の外側にフレーム状の耐酸化膜は
薄いので、素子分離酸化膜形成時に生ずる基板とのスト
レスが媛和され、結晶欠陥を小さくできる。さらに、フ
レーム状耐ヤ化薄膜によってバーズビークは素子領域か
ら退行し、微細加工が可能となり、高に％積比が達成で
きる。(Function) In the present invention, since the mask material left in the element region is angled and the frame-shaped oxidation-resistant film on the outside of this mask material is thin, stress with the substrate that occurs when forming the element isolation oxide film is alleviated. , crystal defects can be reduced. Furthermore, the frame-like anti-yarn film causes the bird's beak to recede from the element region, making microfabrication possible and achieving a high % area ratio.
（実施例） 本発明の一実施例を第１図〜第６図を用いて説明する。(Example) An embodiment of the present invention will be described using FIGS. 1 to 6.
まずＰ型Ｓｉ基板（１００）１に熱酸化膜２を例えば５
００Ａ程度形成した後、ポリシリコン３を例えば４００
０λ程度デボする。次に例えばヒ素を４ Ｑ ｋｅＶ
、 １ｘｔｏ ｃｍ で全面にイオン注入し、さらに
窒化膜４を例えば１５００Ａ程度全面に堆積する（第１
図）。この後、写真蝕刻工程によシレジストをパターニ
ングし、このレジストをマスクに前記窒化膜４をエツチ
ングする（鎮２図）。First, a thermal oxide film 2 is deposited on a P-type Si substrate (100) 1, for example, 5
After forming about 00A, the polysilicon 3 is
Devotion is about 0λ. Next, for example, add arsenic to 4 Q keV
, 1xto cm over the entire surface, and then deposit a nitride film 4 over the entire surface, for example, about 1500A (first
figure). Thereafter, the resist is patterned by a photolithography process, and the nitride film 4 is etched using this resist as a mask (see Figure 2).
次に前記窒化膜４をマスクに前記ポリシリコン３を例え
ばＣＤＥ（ケミカル、ドライ、エツチング）を行うこと
により、斜めにエツチングし、さらにＳｉ基板上の酸化
膜２をエツチングする（第３図）。Next, using the nitride film 4 as a mask, the polysilicon 3 is etched diagonally by, for example, CDE (chemical, dry, etching), and the oxide film 2 on the Si substrate is further etched (FIG. 3).
その後、窒化膜５を例えば減圧気相成長で３００λ程度
堆積する（第４図）。次に例えばＣＶＤ法によシ酸化膜
をｘ５ｏｏＸ程度形成し１、例えば反応性イオンエツチ
ング（几ＩＥ）法によシ全面エツチングして前記酸化膜
を前記窒化膜４，５およびポリシリコン３の側壁段差部
に自己整合的に残飄させこの酸化膜６をマスクとして前
記窒化膜５をエツチングする（第５図）。その後前記酸
化膜を除去し前記窒化膜４，５をマスクに酸化を行なえ
ば第６図のような形状を得、フィールド酸化膜７が形成
される。Thereafter, a nitride film 5 of about 300 λ is deposited, for example, by low pressure vapor phase growth (FIG. 4). Next, for example, a CVD method is used to form a silicon oxide film of approximately 500X, and the entire surface is etched using, for example, a reactive ion etching (IE) method to form the oxide film on the side walls of the nitride films 4, 5 and the polysilicon 3. The nitride film 5 is left on the stepped portion in a self-aligned manner, and the nitride film 5 is etched using the oxide film 6 as a mask (FIG. 5). Thereafter, the oxide film is removed and oxidation is performed using the nitride films 4 and 5 as a mask to obtain a shape as shown in FIG. 6, and a field oxide film 7 is formed.
上記実施例において基板濃度は限定しなかったが、適当
な時期にイオン注入を行ない適当な濃度を設定すること
が可能である。Although the substrate concentration was not limited in the above embodiments, it is possible to set an appropriate concentration by performing ion implantation at an appropriate time.
また、本実施例では、ポリシリコンにイオン注入を行な
い斜めにエツチングを行なったが、この膜質および形成
染付は本実施例に限定されず、本発明の目的を達成する
範朋内で自由に変更できる。Furthermore, in this example, ions were implanted into polysilicon and etching was performed obliquely, but the film quality and formation dyeing are not limited to this example, and can be freely changed within the scope of achieving the purpose of the present invention. Can be changed.
例えば熱酸化ｇ２上に直接窒化膜を堆積した後パターニ
ングされたレジストをマスクに等方性エツチングを行う
ことにより角度をつけてもかまわない。For example, an angle may be created by depositing a nitride film directly on the thermally oxidized g2 and then performing isotropic etching using a patterned resist as a mask.
また、耐酸化性膜として窒化膜以外の材料を使用した場
合にも適用できる。Further, the present invention can also be applied when a material other than a nitride film is used as the oxidation-resistant film.
本発明の製造方法によれば、耐酸化性マスクとして膜厚
の薄い窒化膜を角度をつけたポリシリコン上および基板
上に残すため、フィールド酸化膜形成時にフィールド部
分のエッヂにストレスがかかりにくく、欠陥が生じにく
い、このため良好な分離特性を得ることができる。さら
に耐酸化性マスクとして膜厚の薄い窒化膜を直接基板上
に残すためフィールド酸化膜は横方向へはあｔυ延びず
、かつ十分な膜厚の酸化膜を得ることができる。また本
発明によれば、窒化膜をエツチングする工程以外はすべ
て自己整合的に形成できるため、工程が簡略化でき、微
細化にも有利である。According to the manufacturing method of the present invention, since a thin nitride film is left as an oxidation-resistant mask on the angled polysilicon and on the substrate, stress is less likely to be applied to the edges of the field portion when forming the field oxide film. Defects are less likely to occur, and therefore good separation characteristics can be obtained. Furthermore, since a thin nitride film is left directly on the substrate as an oxidation-resistant mask, the field oxide film does not extend laterally, and an oxide film of sufficient thickness can be obtained. Further, according to the present invention, all steps except the step of etching the nitride film can be formed in a self-aligned manner, so that the steps can be simplified and it is advantageous for miniaturization.
【図面の簡単な説明】
第１図、第２図、第３図、第４図、第５図、第６図は本
発明の一実施例による素子分離製造工程を示す断面図で
ある。
１・・・Ｓｉ基板、２・・・熱酸化膜、３・・・ポリシ
リコン膜、４，５・・・窒化膜、６・・・酸化膜、７・
・・フィールド酸化膜。
代理人 弁理士 則 近 憲 佑
第１図
第２図
第３図
第４図
第５図
第６図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are cross-sectional views showing an element isolation manufacturing process according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Thermal oxide film, 3... Polysilicon film, 4, 5... Nitride film, 6... Oxide film, 7...
...Field oxide film. Agent Patent Attorney Noriyuki ChikaFigure 1Figure 2Figure 3Figure 4Figure 5Figure 6
Claims (4)
する工程と、前記第１の膜を素子領域に対応しかつ角度
を有するようにパターニングする工程と、全面に耐酸化
薄膜を形成した後、前記第１の膜上および前記第１の膜
の側面に隣接してフレーム状の耐酸化性薄膜を形成する
工程と、前記耐酸化性膜をマスクにして半導体基板の酸
化を行なう工程とを備えたことを特徴とする半導体装置
の製造方法。(1) A step of forming a first film on the surface of a semiconductor substrate via an insulating film, a step of patterning the first film so as to correspond to the element region and have an angle, and forming an oxidation-resistant thin film on the entire surface. After the formation, a step of forming a frame-shaped oxidation-resistant thin film on the first film and adjacent to the side surface of the first film, and oxidizing the semiconductor substrate using the oxidation-resistant film as a mask. A method for manufacturing a semiconductor device, comprising the steps of:
る工程と、前記耐酸化性膜を素子領域に対応してパター
ニングする工程と、パターニングされた前記耐酸化性膜
をマスクに前記第１の膜を角度を有するようにパターニ
ングする工程とを備えたことを特徴とする前記特許請求
の範囲第１項記載の半導体装置の製造方法。(2) After forming the first film, a step of forming an oxidation resistant film, a step of patterning the oxidation resistant film corresponding to the element region, and a masking of the patterned oxidation resistant film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: patterning the first film so as to have an angle.
る前記特許請求の範囲第１項記載の半導体装置の製造方
法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the first film is an oxidation-resistant film.
した後素子分離領域の基体を露出させ、しかるのちに前
記耐酸化性薄膜を形成することを特徴とする前記特許請
求の範囲第１項記載の半導体装置の製造方法。(4) After patterning the first film to have an angle, the base of the element isolation region is exposed, and then the oxidation-resistant thin film is formed. A method of manufacturing the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8697687A JPS63253650A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8697687A JPS63253650A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63253650A true JPS63253650A (en) | 1988-10-20 |
Family
ID=13901902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8697687A Pending JPS63253650A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63253650A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100256269B1 (en) * | 1993-12-16 | 2000-05-15 | 김영환 | Semiconductor element field oxidation layer manufacturing method |
| KR100418300B1 (en) * | 1996-12-04 | 2004-04-17 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
-
1987
- 1987-04-10 JP JP8697687A patent/JPS63253650A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100256269B1 (en) * | 1993-12-16 | 2000-05-15 | 김영환 | Semiconductor element field oxidation layer manufacturing method |
| KR100418300B1 (en) * | 1996-12-04 | 2004-04-17 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
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