KR890004400A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR890004400A
KR890004400A KR1019880010455A KR880010455A KR890004400A KR 890004400 A KR890004400 A KR 890004400A KR 1019880010455 A KR1019880010455 A KR 1019880010455A KR 880010455 A KR880010455 A KR 880010455A KR 890004400 A KR890004400 A KR 890004400A
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KR
South Korea
Prior art keywords
semiconductor device
manufacturing
substrate
sputtering
atmosphere
Prior art date
Application number
KR1019880010455A
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English (en)
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KR910009315B1 (ko
Inventor
기자시 시마다
다쯔오 아끼야마
유다가 고시노
Original Assignee
아오이 죠이찌
가부시기가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 아오이 죠이찌, 가부시기가이샤 도오시바 filed Critical 아오이 죠이찌
Publication of KR890004400A publication Critical patent/KR890004400A/ko
Application granted granted Critical
Publication of KR910009315B1 publication Critical patent/KR910009315B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66848Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863Lateral single gate transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/2633Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581Deposition of Schottky electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

요약 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 반도체장치의 제조방법에 사용되는 스핏터링 장치의 일예를 간략적으로 표시한 구성도. 제 2 도(a) 내지(e)는 본 발명의 제조방법의 일실시예에 있어서의 제조공정을 표시한 단면도.

Claims (4)

  1. 스핏터링장치의 스핏터 처리용기 내에서 GaAs기판의 표면을 스핏터 잇칭을 한 다음, 상기 기판을 대기에 바램이 없이, 동일처리 용기내에서 상기 기판표면위에 숏트키 전극재료를 스핏터 퇴적함으로서, 숏트키 전극을 가진 반도체 장치를 제조하는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 상기 스핏터잇칭 전에 GaAs기판을 화학세정하여 두는 것을 특징으로 하는 제 1 항 기재의 반도체장치의 제조방법.
  3. 상기 스핏터잇칭 및 스핏터 퇴적은 각각 불활성 가스 분위기 중에서, 각 대응하여 상기 기판 및 고융 점금속을 타아겟트로 하여 실시하는 것을 특징으로 하는 제 1 항 기재의 반도체장치의 제조방법.
  4. 상기 스핏터잇칭은 Ar의 분위기 중에서 실시하고, 스핏터 잇칭은 Ar+N2의 분위기 중에서 WSi를 타아겟트로 하여 실시하는 것을 특징으로 하는 제 1 항 내지 제 3 항중 어느 일항 기재의 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019880010455A 1987-08-21 1988-08-17 반도체 장치의 제조방법 KR910009315B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-207540 1987-08-21
JP62207540A JPS6450527A (en) 1987-08-21 1987-08-21 Manufacture of semiconductor device
JP?62-207540 1987-08-21

Publications (2)

Publication Number Publication Date
KR890004400A true KR890004400A (ko) 1989-04-21
KR910009315B1 KR910009315B1 (ko) 1991-11-09

Family

ID=16541419

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880010455A KR910009315B1 (ko) 1987-08-21 1988-08-17 반도체 장치의 제조방법

Country Status (3)

Country Link
EP (1) EP0304073A3 (ko)
JP (1) JPS6450527A (ko)
KR (1) KR910009315B1 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106771A (en) * 1991-06-05 1992-04-21 At&T Bell Laboratories GaAs MESFETs with enhanced Schottky barrier
JP2741745B2 (ja) * 1995-03-24 1998-04-22 工業技術院長 半導体電極形成方法および装置
CN102914678B (zh) * 2011-09-26 2013-06-05 北京航天时代光电科技有限公司 罐体式三相光学电压互感器
DE102015101966B4 (de) * 2015-02-11 2021-07-08 Infineon Technologies Austria Ag Verfahren zum Herstellen eines Halbleiterbauelements mit Schottkykontakt und Halbleiterbauelement

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164527A (en) * 1980-05-22 1981-12-17 Toshiba Corp Manufacture of semiconductor device
JPS5749229A (en) * 1980-09-09 1982-03-23 Toshiba Corp Manufacture of gaas device
JPS60173872A (ja) * 1984-02-10 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法
US4585517A (en) * 1985-01-31 1986-04-29 Motorola, Inc. Reactive sputter cleaning of semiconductor wafer

Also Published As

Publication number Publication date
EP0304073A3 (en) 1991-01-30
EP0304073A2 (en) 1989-02-22
JPS6450527A (en) 1989-02-27
KR910009315B1 (ko) 1991-11-09

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