KR870005452A - 금속 실리사이드막 조성비 제어방법 - Google Patents
금속 실리사이드막 조성비 제어방법 Download PDFInfo
- Publication number
- KR870005452A KR870005452A KR1019860007127A KR860007127A KR870005452A KR 870005452 A KR870005452 A KR 870005452A KR 1019860007127 A KR1019860007127 A KR 1019860007127A KR 860007127 A KR860007127 A KR 860007127A KR 870005452 A KR870005452 A KR 870005452A
- Authority
- KR
- South Korea
- Prior art keywords
- metal silicide
- silicide film
- composition ratio
- controlling
- film composition
- Prior art date
Links
- 229910021332 silicide Inorganic materials 0.000 title claims description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims description 19
- 229910052751 metal Inorganic materials 0.000 title claims description 12
- 239000002184 metal Substances 0.000 title claims description 12
- 239000000203 mixture Substances 0.000 title claims 10
- 238000000034 method Methods 0.000 title claims 8
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910045601 alloy Inorganic materials 0.000 claims 3
- 239000000956 alloy Substances 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 229910008486 TiSix Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Silicon Compounds (AREA)
- Physical Vapour Deposition (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1a도는 종래의 MoSix 박막상에 A1를 부착시킨 상태를 표시한 단면도.
제 1b도는 제 1a도에 열처리를 가하여 Si가 A1중에 석출되어있는 상태를 표시한 단면도.
제 1 c도는 제 1b도에서 전면의 A1와 석출Si 제거후의 상태를 표시한 단면도.
제 2 도는 종래의 MoSix 박막이 부착되어 있는 상태를 표시한 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : Si기판 2 : 산화막
3 : 금속 실리사이드막 4 : 알루미늄막
5 : Si석출(도면중 동일부호는 동일 또는 상당부분을 표시한다.)
Claims (7)
- 기판상에 스토이키오메트리(stoichiometry)에서 과잉되게 실리콘을 함유한 금속 실리사이드막을 형성할 경우에 있어서 전기 금속 실리사이드막을 기판상에 부착시킨 후 이 금속 실리사이드막상에 A1 또는 A1 합금막을 부착시키고 열처리를 하여 이 금속 실리사이드막중의 과잉 Si를 A1중에 석출시키므로서 실리사이드의 조성을 제어하는 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- 제 1 항에 있어서 실리사이드가 MoSix일 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- 제 1 항에 있어서 실리사이드가 WSix일 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- 제 1 항에 있어서 실리사이드가 TiSix일 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- 제 1 항에 있어서 실리사이드가 TaSix일 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- 제 1 항에 있어서 열처리가 수소 또는 질소 분위기중이며 더우기 온도가 350∼550℃일 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.
- A1막 또는 A1 합금막에 소망의 패터닝(patterning)을 실시하고 상부에 A1 또는 A1 합금이 있는 부위만의 금속 실리사이드의 실리콘 조성을 저하시켜 저저항화하는 것을 특징으로 하는 금속 실리사이드막 조성비 제어방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60-251061 | 1985-11-09 | ||
| JP251061 | 1985-11-09 | ||
| JP60251061A JPS62111421A (ja) | 1985-11-09 | 1985-11-09 | 金属シリサイド膜組成比制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870005452A true KR870005452A (ko) | 1987-06-09 |
| KR900002619B1 KR900002619B1 (ko) | 1990-04-20 |
Family
ID=17217040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019860007127A KR900002619B1 (ko) | 1985-11-09 | 1986-08-27 | 금속 실리사이드막 조성비 제어방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4983547A (ko) |
| JP (1) | JPS62111421A (ko) |
| KR (1) | KR900002619B1 (ko) |
| DE (1) | DE3636366A1 (ko) |
| GB (1) | GB2183677B (ko) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437011A (en) * | 1987-07-31 | 1989-02-07 | Nec Corp | Manufacture of semiconductor integrated circuit |
| KR960001601B1 (ko) * | 1992-01-23 | 1996-02-02 | 삼성전자주식회사 | 반도체 장치의 접촉구 매몰방법 및 구조 |
| US5418188A (en) * | 1991-09-05 | 1995-05-23 | International Business Machines Corporation | Method for controlled positioning of a compound layer in a multilayer device |
| US5358574A (en) * | 1993-11-22 | 1994-10-25 | Midwest Research Institute | Dry texturing of solar cells |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
| US5725739A (en) | 1996-07-08 | 1998-03-10 | Micron Technology, Inc. | Low angle, low energy physical vapor deposition of alloys |
| DE19742972A1 (de) * | 1997-09-29 | 1999-04-08 | Siemens Ag | Verfahren zur Ausbildung eines niederohmigen Leitbahnbereichs auf einem Halbleitersubstrat |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3382568A (en) * | 1965-07-22 | 1968-05-14 | Ibm | Method for providing electrical connections to semiconductor devices |
| US4332839A (en) * | 1978-12-29 | 1982-06-01 | Bell Telephone Laboratories, Incorporated | Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide |
| JPS5735318A (en) * | 1980-08-12 | 1982-02-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4337476A (en) * | 1980-08-18 | 1982-06-29 | Bell Telephone Laboratories, Incorporated | Silicon rich refractory silicides as gate metal |
| GB2128636B (en) * | 1982-10-19 | 1986-01-08 | Motorola Ltd | Silicon-aluminium alloy metallization of semiconductor substrate |
| US4443930A (en) * | 1982-11-30 | 1984-04-24 | Ncr Corporation | Manufacturing method of silicide gates and interconnects for integrated circuits |
-
1985
- 1985-11-09 JP JP60251061A patent/JPS62111421A/ja active Pending
-
1986
- 1986-08-27 KR KR1019860007127A patent/KR900002619B1/ko not_active IP Right Cessation
- 1986-10-25 DE DE19863636366 patent/DE3636366A1/de active Granted
- 1986-11-06 GB GB8626523A patent/GB2183677B/en not_active Expired
-
1988
- 1988-10-20 US US07/260,390 patent/US4983547A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| GB8626523D0 (en) | 1986-12-10 |
| US4983547A (en) | 1991-01-08 |
| JPS62111421A (ja) | 1987-05-22 |
| GB2183677B (en) | 1989-12-20 |
| GB2183677A (en) | 1987-06-10 |
| DE3636366C2 (ko) | 1993-06-03 |
| DE3636366A1 (de) | 1987-05-14 |
| KR900002619B1 (ko) | 1990-04-20 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 19970415 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |