KR870002638A - Method for forming dielectric thin film and semiconductor device comprising the thin film - Google Patents

Method for forming dielectric thin film and semiconductor device comprising the thin film Download PDF

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KR870002638A
KR870002638A KR1019860007073A KR860007073A KR870002638A KR 870002638 A KR870002638 A KR 870002638A KR 1019860007073 A KR1019860007073 A KR 1019860007073A KR 860007073 A KR860007073 A KR 860007073A KR 870002638 A KR870002638 A KR 870002638A
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thin film
silicon
oxide
aluminum
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KR1019860007073A
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KR940005290B1 (en
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카가노위츠 그르제고르쯔
월터 로빈슨 존
챠알스 이프리 알프레드
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글렌 에이취. 브르스틀
알씨. 에이 코오포레이숀
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/027—Graded interfaces
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C23C14/081—Oxides of aluminium, magnesium or beryllium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용 없음No content

Description

유전체 박막을 형성하는 방법 및 그 박막을 포함하는 반도체 장치Method for forming dielectric thin film and semiconductor device comprising the thin film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 장치용 유전체 박막을 형성하는데 적합한 장치의 단면도.1 is a cross-sectional view of a device suitable for forming the dielectric thin film for the device of the present invention.

제2도는 본 발명의 반도체 장치의 단면도.2 is a cross-sectional view of a semiconductor device of the present invention.

제3도는 유전체 박막이 플라즈마 성장된 제1영역을 가진 장치에 있어서 임계전압의 변화를 예시한 그래프,3 is a graph illustrating a change in threshold voltage in a device having a first region in which a dielectric thin film is plasma grown;

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

(12) 진공실 (14) 전극 (16) 전원 (18, 22) 자석(12) vacuum chamber (14) electrode (16) power source (18, 22) magnet

(20) 타겟 (24) 진공실 출구 (26) 제1입구 (28) 제2입구(20) Target (24) Vacuum Room Outlet (26) First Inlet (28) Second Inlet

(30) 기관 (32) 장착판 (40) 트랜지스터 (42) 유리기판(30) Engine (32) Mounting plate (40) Transistor (42) Glass substrate

(44) 실리콘층 (46) 유전체 (48) 제1영역 (50) 제2영역(44) Silicon Layer (46) Dielectric (48) First Area (50) Second Area

(56) 소스영역 (58) 드레인영역 (60) 채널영역(56) Source Area (58) Drain Area (60) Channel Area

Claims (15)

(가) 실리콘 산화물을 포함하는 박막의 제1영역을 형성하도록 산소함유 분위기에서 실리콘 몸체의 표면을 산화시키는 단계,(A) oxidizing the surface of the silicon body in an oxygen-containing atmosphere to form a first region of the thin film comprising silicon oxide, (나) 상기 제1영역위에 실리콘과 알루미늄 산화물의 혼합물을 포함하는 제2영역을 형성하도록 알루미늄을 스퍼터링하는 단계,(B) sputtering aluminum to form a second region over said first region comprising a mixture of silicon and aluminum oxide, (다) 알루미늄의 반응성 스퍼터링에 의해 상기 제2영역위에 실질적으로 알루미늄 산화물로된 제3영역을 형성하는 단계를 포함하는 것을 특징으로 하는 실리콘 몸체상에 유전체 박막을 형성하는 방법.(C) forming a third region of substantially aluminum oxide over said second region by reactive sputtering of aluminum. 제1항에 있어서,The method of claim 1, 상기 (가) 단계는 산소 함유 플라즈마에서 실행되고, 그 플라즈마는 상기 알루미늄의 반응성 스퍼터링을 행하도록 (나) 및 (다) 단계를 통해서 유지되는 것을 특징으로하는 방법.Wherein step (a) is performed in an oxygen-containing plasma, and the plasma is maintained through steps (b) and (c) to effect reactive sputtering of the aluminum. 제2항에 있어서,The method of claim 2, 상기 분위기의 온도가 약 300℃ 이하로 유지되는 것을 특징으로하는 방법.The temperature of the atmosphere is maintained at about 300 ° C. or less. 제2항에 있어서,The method of claim 2, 상기 (가) 단계는 열적 산화에 의해 실리콘상에 일정 두께의 이산화규소를 형성하는 것에 의하여 선행되는 것을 특징으로하는 방법.The step (a) is preceded by the formation of silicon dioxide of a certain thickness on silicon by thermal oxidation. 제2항에 있어서,The method of claim 2, 플라즈마는 약 1내지 15Wat/cm²의 유효 전력 밀도를 갖는 것을 특징으로하는 방법.And the plasma has an effective power density of about 1 to 15 Watt / cm 2. 제1항에 있어서,The method of claim 1, 상기 (가) 단계는 열적 산화에 의하여 실행되는 것을 특징으로 하는 방법.The step (a) is characterized in that carried out by thermal oxidation. 제6항에 있어서,The method of claim 6, 열적 산화는 약 600℃의 온도에서 실행되는 것을 특징으로하는 방법.Thermal oxidation is performed at a temperature of about 600 ° C. 제1항의 방법에 의하여 형성된 산화물 유전체 박막을 포함하는 반도체 장치.A semiconductor device comprising an oxide dielectric thin film formed by the method of claim 1. 반도체의 몸체와 유전체의 박막에 의해 분리된 전극을 포함하는 반도체 장치에 있어서, 상기 유전체 박막이 실리콘 산화물을 포함하는 제1영역과 ;A semiconductor device comprising a body of a semiconductor and an electrode separated by a thin film of a dielectric, said semiconductor device comprising: a first region comprising a silicon oxide; 실리콘 및 알루미늄 산화물의 혼합물을 포함하는데, 상기 제1영역으로부터의 거리의 증가에 따라 실리콘 산화물의 농도는 감소하고 알루미늄 산화물의 농도는 증가하는 상기 제1영역위에 놓인 제2영역과 ;A second region overlying said first region, wherein the concentration of silicon oxide decreases and the concentration of aluminum oxide increases with increasing distance from said first region; 알루미늄 산화물을 포함하는 상기 제2영역위에 놓인 제3영역을 갖는 것을 특징으로하는 반도체 장치.And a third region overlying said second region comprising aluminum oxide. 제8항에 있어서 ,The method of claim 8, 상기 제1영역이 약 5내지 100nm의 두께를 가진 것을 특징으로하는 장치.And wherein said first region has a thickness of about 5 to 100 nm. 제9항에 있어서,The method of claim 9, 상기 제1영역이 플라즈마 성장되고 약 5내지 20nm의 두께를 가진 것을 특징으로하는 장치.And wherein said first region is plasma grown and has a thickness of about 5 to 20 nm. 제8항에 있어서,The method of claim 8, 상기 제2영역은 약 2내지 30nm의 두께를 가진 것을 특징으로하는 장치.And said second region has a thickness of about 2 to 30 nm. 제8항에 있어서,The method of claim 8, 상기 제3영역은 약 10내지 100nm의 두께를 가진것을 특징으로하는 장치.And said third region has a thickness of about 10 to 100 nm. 제8항에 있어서,The method of claim 8, 상기 장치는 금속 산화물 반도체 전계효과 트랜지스터인 것을 특징으로하는 장치.And the device is a metal oxide semiconductor field effect transistor. 제13항에 있어서,The method of claim 13, 상기 제1영역은 열적으로 성장된 약 6nm두께의 실리콘 산화물을 가진것을 특징으로하는 장치.Wherein said first region has about 6 nm thick silicon oxide thermally grown. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860007073A 1985-08-27 1986-08-26 Method of forming a dielectric film and semiconductor device including said film KR940005290B1 (en)

Applications Claiming Priority (2)

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US76997585A 1985-08-27 1985-08-27
US769,975 1985-08-27

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KR870002638A true KR870002638A (en) 1987-04-06
KR940005290B1 KR940005290B1 (en) 1994-06-15

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JP (1) JPS6358843A (en)
KR (1) KR940005290B1 (en)
DE (1) DE3628399A1 (en)
GB (1) GB2179679B (en)
SG (1) SG134792G (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310610A (en) * 1988-05-07 1994-05-10 Sharp Kabushiki Kaisha Silicon micro sensor and manufacturing method therefor
JPH0748564B2 (en) * 1988-05-07 1995-05-24 シャープ株式会社 Silicon micro sensor
US5387530A (en) * 1993-06-29 1995-02-07 Digital Equipment Corporation Threshold optimization for soi transistors through use of negative charge in the gate oxide
KR20010005788A (en) * 1997-03-28 2001-01-15 미가쿠 다카하시 Method for manufacturing magnetoresistance element
KR100480756B1 (en) * 2002-08-02 2005-04-06 한국화학연구원 Process for preparing aluminum oxide thin film

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* Cited by examiner, † Cited by third party
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US3287243A (en) * 1965-03-29 1966-11-22 Bell Telephone Labor Inc Deposition of insulating films by cathode sputtering in an rf-supported discharge
GB1204544A (en) * 1966-09-02 1970-09-09 Hitachi Ltd Semiconductor device and method of manufacturing the same
US3502950A (en) * 1967-06-20 1970-03-24 Bell Telephone Labor Inc Gate structure for insulated gate field effect transistor
JPS523782B2 (en) * 1972-12-19 1977-01-29
DE2452289A1 (en) * 1974-11-04 1976-05-06 Siemens Ag SEMICONDUCTOR COMPONENT
JPS5527644A (en) * 1978-08-17 1980-02-27 Nec Corp Multi-layer wiring type semiconductor device
JPS5572043A (en) * 1978-11-27 1980-05-30 Fujitsu Ltd Preparation of semiconductor device
DE3122382A1 (en) * 1981-06-05 1982-12-23 Ibm Deutschland METHOD FOR PRODUCING A GATE INSULATION LAYER STRUCTURE AND USE OF SUCH A STRUCTURE

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GB8620609D0 (en) 1986-10-01
SG134792G (en) 1993-03-12
KR940005290B1 (en) 1994-06-15
GB2179679B (en) 1990-01-04
JPS6358843A (en) 1988-03-14
DE3628399A1 (en) 1987-03-05
GB2179679A (en) 1987-03-11

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