JPS5893277A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPS5893277A JPS5893277A JP19061181A JP19061181A JPS5893277A JP S5893277 A JPS5893277 A JP S5893277A JP 19061181 A JP19061181 A JP 19061181A JP 19061181 A JP19061181 A JP 19061181A JP S5893277 A JPS5893277 A JP S5893277A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- gate
- fet
- gate oxidized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 238000000034 method Methods 0.000 description 11
- 239000011521 glass Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
（１）発明の属する技術分野
本発明け、シリコン薄膜を能動領域として用いる電界効
果トランジスタ（ｒｇ’ｒ）の製造方法に係り、特にシ
リコン薄膜および、ゲート絶縁膜である二酸化シリコン
膜を同一装置内で所定の厚さだけ連続的に堆積すること
により、ゲート酸化膜−シリ造方法に関する。Detailed Description of the Invention (1) Technical field to which the invention pertains The present invention relates to a method for manufacturing a field effect transistor (RG'R) using a silicon thin film as an active region, and particularly relates to a method for manufacturing a field effect transistor (RG'R) using a silicon thin film and a gate insulating film. The present invention relates to a method for forming a gate oxide film by continuously depositing a silicon dioxide film to a predetermined thickness in the same apparatus.
（２）従来技術とその問題虞
従来、クリコンを能動領域として用いたＦＥＴの製造方
法は、 Ｆ１３Ｔのチャンネル部分と、ゲート絶縁膜
の形成は当然のことながら全く別工程で行なわれている
。その理由は、基板として用いるシリコンウェハーが、
強酸処理、高温処理に容易に耐えられることであり、ゲ
ート絶縁膜としては、基板シリコンウェハーを高温熱酸
化することにより形成している。またＦＥｌｉＴのゲー
ト絶縁膜としては、このように形成した膜が最も安定な
低しきい値を与えるものとされている。(2) Prior Art and its Problems Conventionally, in the method of manufacturing FETs using cryocon as an active region, the formation of the F13T channel portion and the gate insulating film are naturally performed in completely separate steps. The reason is that the silicon wafer used as the substrate is
It can easily withstand strong acid treatment and high temperature treatment, and the gate insulating film is formed by high temperature thermal oxidation of the substrate silicon wafer. Furthermore, as a gate insulating film for FELiT, a film formed in this manner is said to provide the most stable low threshold voltage.
しかし、基板として非晶質物質、たとえばガラス板を弔
い、シリコン薄膜として、多結晶シリコン膜を用いて、
Ｆｇ’ｌ”を製造する場合、どのようなガラス板を用い
ても、その使用温度は、高々６５０°Ｃ以下でちり＊
（（てｓ 強酸、強アルカリ処理も行なえないという
制約がある。従って、ゲート絶縁膜は、上述のような熱
酸化膜を用いることは不可能でちり、スパッタリング法
により、二酸化シリコンあるいはアルミナ、あるいは窒
化シリコン等を堆積して用いるか、（にはＣＶＤ法によ
って絶縁膜を形成する以外に方法は無かった。However, if an amorphous material such as a glass plate is used as the substrate and a polycrystalline silicon film is used as the silicon thin film,
When manufacturing "Fg'l", no matter what kind of glass plate is used, the operating temperature must be no more than 650°C and dust will not form*.
(There is a restriction that strong acid or strong alkali treatment cannot be performed. Therefore, it is impossible to use a thermal oxide film as described above for the gate insulating film. Instead, silicon dioxide, alumina, or There was no other method other than depositing silicon nitride or the like or forming an insulating film by CVD.
Ｌ記の場合、多結晶シリコン暎の形成と、ゲート絶縁膜
の形成とは全く別の装置あるいは、同一装置を用いる場
合も非連続的（で行なわれて訃り、Ｆ’ｆ（Ｔとして最
も重要なゲート絶縁膜−多結晶シリコン界面が、空気中
に晒されてしまい、水蒸気の吸着等の汚染が界面に残さ
れてしまう。更に、基板かガラスであるか由に１強酸、
強アルカリによる処理が行なえないため、界面にアセカ
リ象属、重金属の汚染が残され、 Ｆ’ＥＴのしきい
値に不安定性を与えてしまう。In the case of L, the formation of the polycrystalline silicon layer and the formation of the gate insulating film are performed in completely different equipment, or even if the same equipment is used, they are performed discontinuously (F'f (T) The important gate insulating film-polycrystalline silicon interface is exposed to the air, and contamination such as adsorption of water vapor remains on the interface.Furthermore, because the substrate is glass, strong acids,
Since treatment with a strong alkali cannot be carried out, contamination with acetic acid and heavy metals remains at the interface, causing instability in the F'ET threshold.
（３）発明の目的及び概要
本発明は上記の欠点を大幅に改善したものである。即ち
本発明は、非晶質基板上の多結晶シリコン膜とゲート酸
化膜を同一装置で連続１〜で形成することにより、多結
晶シリコンゲート酸化膜界面の汚染を皆無にしたことで
ある。(3) Purpose and outline of the invention The present invention significantly improves the above-mentioned drawbacks. That is, the present invention completely eliminates contamination of the polycrystalline silicon gate oxide film interface by forming a polycrystalline silicon film and a gate oxide film on an amorphous substrate successively in the same device.
（４）発明の実施例 以下に図を参照して本発明の実施例を述べる。(4) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第１図から、第３図までが本発明の主旨であり、第１図
は非晶質基板として超硬質ガラス（１）を示しており、
本実施例ではバリウム硼珪酸ガラス（除冷点６３９°Ｃ
２軟化点８４４°０）を用いた。本発明では、多結晶シ
リコンおよび二酸化シリコンの堆積装置として、５ｉＨ
４ｔｒよびＳｉＨ４＋０２を常圧で熱分解させる装置、
いわゆる常圧ＣＶＤ装置を用いている。第２図は上述の
ガラス基板（１）を常圧ＣＶＤ装置内に設置し、 ８
１＋１４の熱分解により、多結晶シリコン膜（２）を０
．６／１＋ｎの厚さで堆積した状態を示す。常ＥＥ Ｃ
ＶＤ法により所定の厚さの多結晶シリコン膜を堆積し終
ったら、同一装置内に新らだに０２ガスを導入し、 ５
ｉｌｔ４＋ｏ２の混合ガスを熱分叫することＩＣｌ：
リ、第３図に示す如く、所定の厚さの二酸化シリコン膜
（３）を多結晶シリコン膜（２）上に堆積する。The gist of the present invention is shown in FIGS. 1 to 3, and FIG. 1 shows ultra-hard glass (1) as an amorphous substrate.
In this example, barium borosilicate glass (annealing point 639°C
2 softening point 844°0) was used. In the present invention, a 5iH
A device for thermally decomposing 4tr and SiH4+02 at normal pressure,
A so-called normal pressure CVD device is used. Figure 2 shows the above-mentioned glass substrate (1) installed in an atmospheric pressure CVD apparatus.
Polycrystalline silicon film (2) is reduced to 0 by thermal decomposition of 1+14.
．． A state in which the film is deposited to a thickness of 6/1+n is shown. Always EE C
After depositing a polycrystalline silicon film of a predetermined thickness by the VD method, a new 02 gas is introduced into the same apparatus, and 5
Thermal separation of the mixed gas of ilt4+o2 ICl:
As shown in FIG. 3, a silicon dioxide film (3) of a predetermined thickness is deposited on the polycrystalline silicon film (2).
この膜は１畑Ｔのゲート・°酸化膜となるものでちり、
本実施例では、Ｑ２．ａｍの厚さにした。この一連の１
１．１
堆積１程が、本発明の主旨であり、［ｉ”Ｅ’ｌ’の能
動領１歳となる多結晶シリコン グートリ２化暎界間け
、王程中何らの汚染を受けることが無い。This film becomes the gate/° oxide film of 1 field T and is dusty.
In this embodiment, Q2. It was made to have a thickness of am. This series of 1
1.1 The first stage of deposition is the gist of the present invention, and the active region of the polycrystalline silicon layer is not contaminated during the first stage.
第４図、第５図は、本発明により作製した二酸化シリコ
ン−多結晶シリコン−ガラス基板をｎチャンネルエンハ
ンスメント型ＭＯ８Ｆ’ＥＴに製作する工程を示す。第
４図１ｄ、上記基板上に所定の寸法の島状二’、！化シ
リコンー多結晶シリコン領域を残し、アルミニウムゲー
ト（４）を形成したものである。本実症例のＰＥＴはア
ルミニウムゲートセルファライン方式で作製するため、
アルミゲート（４）をマスクにして燐イオン注入（５）
を注入歇３Ｘ１０１５／Ｃｒ／を加速電ＦＥ ：２００
ＫｅＶで行なっている。この策件では、ノース、ドレ
ーンとなる領域の注入燐原子分解け、濃度の゛クーク位
置が二酸化シリコン−多結晶シリコン界面にあり、濃度
は２，１ ｘｌ ｇ２０／７に達している。注入燐原子
の電気的活性化は、５００”０、窒素中で２０時間の熱
処理を行ない、その結果、ノース（６）、ドレーン（７
）領域は、完全なｎ層となり、ノート抵抗値は８００〜
１ｎｏｏＱ／・１の範囲であった。FIGS. 4 and 5 show the process of fabricating a silicon dioxide-polycrystalline silicon-glass substrate produced according to the present invention into an n-channel enhancement type MO8F'ET. FIG. 4 1d, two islands of predetermined dimensions on the substrate, ! The silicon oxide-polycrystalline silicon region is left and an aluminum gate (4) is formed. Since the PET in this actual case is manufactured using the aluminum gate self-line method,
Phosphorus ion implantation using the aluminum gate (4) as a mask (5)
Injection rate 3X1015/Cr/acceleration electric current FE: 200
This is done using KeV. In this case, the concentration of the implanted phosphorus atoms in the regions that will become the north and drain regions is located at the silicon dioxide-polycrystalline silicon interface, and the concentration reaches 2.1 x l g20/7. Electrical activation of the implanted phosphorus atoms was carried out by heat treatment for 20 hours in nitrogen at 500"0, resulting in the north (6), drain (7)
) region becomes a complete n layer, and the note resistance value is 800~
It was in the range of 1nooQ/·1.
第５図は、形成されたソース（６）、ドレーン（力領域
へのアルミニウムコンタクト形成状態を示し、コンタク
トホールを二酸化シリコン（３）に開孔した後、所定の
寸法のソース（８）、ドレーン（９）電極・配線を形成
する。Figure 5 shows the state of forming aluminum contacts to the formed source (6) and drain regions. After contact holes are opened in silicon dioxide (3), the source (8) and drain of predetermined dimensions are (9) Form electrodes and wiring.
（５）発明の効果
本発明の実施例で得られたｎチャンネルエンハンスメン
ト型ＭＯ８ｌｌｉ’１１８Ｔの電気的特性は、しきい値
（ＶＴ）８（Ｖ）、実効移動１ｆ （） １．０ （ｍ
／Ｎ’ ２ｅｃ ） を示し、峨田−電流特性に不安定
なヒステリシス等は全く観測されず、低しきい値安定な
Ｆ’？ｊＴが製造出来だ。(5) Effects of the invention The electrical characteristics of the n-channel enhancement type MO8lli'118T obtained in the embodiment of the present invention are as follows: threshold value (VT) 8 (V), effective movement 1f () 1.0 (m
/N' 2ec ), no unstable hysteresis or the like was observed in the Asada-current characteristics, and a stable low threshold F'? jT can be manufactured.
（６）発明の変形例
本発明の実権例では、堆積装置として、ＳｉＨ４の熱分
解による常Ｅ ＣＶＤ装置を用いたが、減圧ＣＶＤ装置
でも実施は可能であり、更に、スパッタリング法あるい
はプラズマＣＶＤ法でも本発明が実施出来ることはぽう
までも無い。また、ゲート絶縁膜として、二酸化シリコ
ン膜を例に示したが窒化シリコン膜、アルミナ膜五酸化
タンタル膜等を用いた実権も可能である。(6) Modified Examples of the Invention In the practical examples of the present invention, a conventional ECVD apparatus using thermal decomposition of SiH4 was used as a deposition apparatus, but a low pressure CVD apparatus can also be used. However, there is no way that the present invention can be implemented. Further, although a silicon dioxide film is shown as an example as the gate insulating film, it is also possible to use a silicon nitride film, an alumina film, a tantalum pentoxide film, or the like.
哨１図〜第３図は、ガラス基板上に同一装置内で連続的
に多結晶シリコン噛、ゲート酸化膜を吐積する工程を示
し、第４図、第５図は、アルミニウムゲートをマスクと
したイオン注入によるセルファライン方式でＭＯ８＆″
Ｅ′Ｆを製作する工程図である。
１・・・非晶質基板（ガラス）、２・・・多結晶シリコ
ン啼、３・・・ゲート絶縁膜（二、唆化シリコン暎）、
４・・・アルミニウムゲート、５・・・イオンビーム、
６．７・・・ｎ＋ンソー・ドレイン領域、８，９・・・
ソースドレーン電極。
第１図
第２図
第８図
第４区
々
１：′１
第５図Figures 1 to 3 show the process of successively depositing polycrystalline silicon and gate oxide films on a glass substrate in the same device, and Figures 4 and 5 show the process of depositing a gate oxide film on a glass substrate using an aluminum gate as a mask. MO8 &'' by self-line method using ion implantation
It is a process diagram for manufacturing E'F. 1...Amorphous substrate (glass), 2...Polycrystalline silicon, 3...Gate insulating film (2. Insulated silicon),
4... Aluminum gate, 5... Ion beam,
6.7...n+ drain region, 8,9...
source drain electrode. Figure 1 Figure 2 Figure 8 Figure 4 Section 1:'1 Figure 5
Claims (1)
て用いた電界効果トランジスタを形成する際、所定の厚
さのシリコン薄膜啼を非晶質基板上（Ｃ堆積し、引き続
き同−装置内で連続的にｌｉ’？３’ｒWhen forming a field effect transistor using a silicon thin film deposited on an amorphous substrate as an active region, a silicon thin film of a predetermined thickness is deposited on the amorphous substrate (C is deposited and then in the same apparatus). Continuously li'?3'r
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19061181A JPS5893277A (en) | 1981-11-30 | 1981-11-30 | Manufacture of thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19061181A JPS5893277A (en) | 1981-11-30 | 1981-11-30 | Manufacture of thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893277A true JPS5893277A (en) | 1983-06-02 |
Family
ID=16260946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19061181A Pending JPS5893277A (en) | 1981-11-30 | 1981-11-30 | Manufacture of thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60241268A (en) * | 1984-05-16 | 1985-11-30 | Seiko Epson Corp | Manufacture of thin film transistor |
| US6221701B1 (en) | 1984-05-18 | 2001-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and its manufacturing method |
-
1981
- 1981-11-30 JP JP19061181A patent/JPS5893277A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60241268A (en) * | 1984-05-16 | 1985-11-30 | Seiko Epson Corp | Manufacture of thin film transistor |
| US6221701B1 (en) | 1984-05-18 | 2001-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and its manufacturing method |
| US6660574B1 (en) | 1984-05-18 | 2003-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming a semiconductor device including recombination center neutralizer |
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