KR20190045909A - 백사이드 바디 콘택트를 갖는 딥 트렌치 능동 디바이스 - Google Patents

백사이드 바디 콘택트를 갖는 딥 트렌치 능동 디바이스 Download PDF

Info

Publication number
KR20190045909A
KR20190045909A KR1020197006280A KR20197006280A KR20190045909A KR 20190045909 A KR20190045909 A KR 20190045909A KR 1020197006280 A KR1020197006280 A KR 1020197006280A KR 20197006280 A KR20197006280 A KR 20197006280A KR 20190045909 A KR20190045909 A KR 20190045909A
Authority
KR
South Korea
Prior art keywords
backside
gate
layer
coupled
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020197006280A
Other languages
English (en)
Korean (ko)
Inventor
시난 고테펠리
스티브 파넬리
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20190045909A publication Critical patent/KR20190045909A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H01L27/1211—
    • H01L21/76251—
    • H01L23/481—
    • H01L23/5223—
    • H01L23/66—
    • H01L29/0649—
    • H01L29/66795—
    • H01L29/7851—
    • H01L29/78615—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/218—Through-semiconductor vias, e.g. TSVs in silicon-on-insulator [SOI] wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
KR1020197006280A 2016-09-06 2017-08-03 백사이드 바디 콘택트를 갖는 딥 트렌치 능동 디바이스 Ceased KR20190045909A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/257,823 2016-09-06
US15/257,823 US9812580B1 (en) 2016-09-06 2016-09-06 Deep trench active device with backside body contact
PCT/US2017/045349 WO2018048529A1 (en) 2016-09-06 2017-08-03 Deep trench active device with backside body contact

Publications (1)

Publication Number Publication Date
KR20190045909A true KR20190045909A (ko) 2019-05-03

Family

ID=59684050

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197006280A Ceased KR20190045909A (ko) 2016-09-06 2017-08-03 백사이드 바디 콘택트를 갖는 딥 트렌치 능동 디바이스

Country Status (7)

Country Link
US (1) US9812580B1 (https=)
EP (1) EP3510636A1 (https=)
JP (1) JP2019530218A (https=)
KR (1) KR20190045909A (https=)
CN (1) CN109791948A (https=)
BR (1) BR112019003900A2 (https=)
WO (1) WO2018048529A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210148843A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 에어 갭을 갖는 반도체 디바이스 및 그 제조 방법
KR20250015906A (ko) * 2023-07-25 2025-02-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 금속 산화물 반도체 커패시터 및 이를 제조하는 방법

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504240B (zh) * 2018-05-16 2021-08-13 联华电子股份有限公司 半导体元件及其制造方法
CN109524355B (zh) * 2018-10-30 2020-11-10 上海集成电路研发中心有限公司 一种半导体器件的结构和形成方法
CN109545785B (zh) * 2018-10-31 2023-01-31 上海集成电路研发中心有限公司 一种半导体器件结构和制备方法
CN109616472B (zh) * 2018-12-14 2022-11-15 上海微阱电子科技有限公司 一种半导体器件结构和形成方法
CN109545802B (zh) * 2018-12-14 2021-01-12 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法
EP3853895B1 (en) * 2019-01-30 2023-11-22 Yangtze Memory Technologies Co., Ltd. Capacitor structure having vertical diffusion plates
CN109891585B (zh) * 2019-01-30 2020-03-27 长江存储科技有限责任公司 具有垂直扩散板的电容器结构
KR102642279B1 (ko) * 2019-02-18 2024-02-28 양쯔 메모리 테크놀로지스 씨오., 엘티디. 새로운 커패시터 구조 및 이를 형성하는 방법
US11355410B2 (en) * 2020-04-28 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices
TWI741935B (zh) 2020-04-28 2021-10-01 台灣積體電路製造股份有限公司 半導體元件與其製作方法
US11349004B2 (en) * 2020-04-28 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Backside vias in semiconductor device
US11251308B2 (en) 2020-04-28 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
DE102020122151A1 (de) * 2020-04-28 2021-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
US20240097657A1 (en) * 2022-09-16 2024-03-21 Apple Inc. Systems and methods for impedance tuning
CN120280431B (zh) * 2025-06-04 2025-09-30 长飞先进半导体(武汉)有限公司 半导体器件及制作方法、功率模块、功率转换电路和车辆

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2948018B2 (ja) * 1992-03-17 1999-09-13 三菱電機株式会社 半導体装置およびその製造方法
US5889298A (en) 1993-04-30 1999-03-30 Texas Instruments Incorporated Vertical JFET field effect transistor
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
US6861701B2 (en) 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
JP4869546B2 (ja) * 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
DE102005030585B4 (de) * 2005-06-30 2011-07-28 Globalfoundries Inc. Halbleiterbauelement mit einem vertikalen Entkopplungskondensator und Verfahren zu seiner Herstellung
JP2009088241A (ja) * 2007-09-28 2009-04-23 Renesas Technology Corp 半導体装置およびその製造方法
JP5487625B2 (ja) * 2009-01-22 2014-05-07 ソニー株式会社 半導体装置
US8395880B2 (en) * 2010-03-30 2013-03-12 Medtronic, Inc. High density capacitor array patterns
US8735984B2 (en) * 2010-07-06 2014-05-27 Globalfoundries Singapore PTE, LTD. FinFET with novel body contact for multiple Vt applications
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8735993B2 (en) * 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US9148194B2 (en) * 2012-07-07 2015-09-29 Skyworks Solutions, Inc. Radio-frequency switch system having improved intermodulation distortion performance
US20160172527A1 (en) * 2012-12-03 2016-06-16 Sandia Corporation Photodetector with Interdigitated Nanoelectrode Grating Antenna
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator
US9478507B2 (en) * 2013-03-27 2016-10-25 Qualcomm Incorporated Integrated circuit assembly with faraday cage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210148843A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 에어 갭을 갖는 반도체 디바이스 및 그 제조 방법
US11830769B2 (en) 2020-05-28 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with air gaps and method of fabrication thereof
US12463092B2 (en) 2020-05-28 2025-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with air gaps and method of fabrication thereof
KR20250015906A (ko) * 2023-07-25 2025-02-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 금속 산화물 반도체 커패시터 및 이를 제조하는 방법

Also Published As

Publication number Publication date
CN109791948A (zh) 2019-05-21
EP3510636A1 (en) 2019-07-17
BR112019003900A2 (pt) 2019-05-21
JP2019530218A (ja) 2019-10-17
WO2018048529A1 (en) 2018-03-15
US9812580B1 (en) 2017-11-07

Similar Documents

Publication Publication Date Title
KR102054924B1 (ko) 듀얼-사이디드 프로세싱을 갖는 로직 회로 블록 레이아웃들
US9812580B1 (en) Deep trench active device with backside body contact
EP3449503B1 (en) Integrated radio frequency circuit structure
EP3443592B1 (en) Switch device performance improvement through multisided biased shielding
KR102675753B1 (ko) 후면 실리사이드화에 의한 벌크 층 전사 프로세싱
US9917062B1 (en) Self-aligned transistors for dual-side processing
US10043752B2 (en) Substrate contact using dual sided silicidation
US10290579B2 (en) Utilization of backside silicidation to form dual side contacted capacitor
CA3073721C (en) Bulk layer transfer processing with backside silicidation
HK40009868A (en) Logic circuit block layouts with dual-sided processing
HK40009868B (en) Logic circuit block layouts with dual-sided processing

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000