KR20190039714A - 듀얼 사이드 콘택 커패시터를 형성하기 위한 백사이드 실리사이드화의 활용 - Google Patents

듀얼 사이드 콘택 커패시터를 형성하기 위한 백사이드 실리사이드화의 활용 Download PDF

Info

Publication number
KR20190039714A
KR20190039714A KR1020197004314A KR20197004314A KR20190039714A KR 20190039714 A KR20190039714 A KR 20190039714A KR 1020197004314 A KR1020197004314 A KR 1020197004314A KR 20197004314 A KR20197004314 A KR 20197004314A KR 20190039714 A KR20190039714 A KR 20190039714A
Authority
KR
South Korea
Prior art keywords
layer
backside
circuit structure
integrated circuit
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020197004314A
Other languages
English (en)
Korean (ko)
Inventor
시난 고크테펠리
플레이먼 바실레브 코레브
마이클 앤드류 스튜버
리처드 햄몬드
쉬쿤 구
스티브 파넬리
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20190039714A publication Critical patent/KR20190039714A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H01L23/66
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435Cross-sectional shapes or dispositions of interconnections
    • H01L23/5223
    • H01L23/5283
    • H01L23/53209
    • H01L27/1203
    • H01L28/40
    • H01L29/0649
    • H01L29/66181
    • H01L29/94
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/01Manufacture or treatment
    • H10D1/045Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/62Capacitors having potential barriers
    • H10D1/66Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496Capacitor integral with wiring layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/20Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H01L2223/6677
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/20Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020197004314A 2016-08-18 2017-07-14 듀얼 사이드 콘택 커패시터를 형성하기 위한 백사이드 실리사이드화의 활용 Ceased KR20190039714A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/240,952 2016-08-18
US15/240,952 US9847293B1 (en) 2016-08-18 2016-08-18 Utilization of backside silicidation to form dual side contacted capacitor
PCT/US2017/042213 WO2018034756A1 (en) 2016-08-18 2017-07-14 Utilization of backside silicidation to form dual side contacted capacitor

Publications (1)

Publication Number Publication Date
KR20190039714A true KR20190039714A (ko) 2019-04-15

Family

ID=59416818

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197004314A Ceased KR20190039714A (ko) 2016-08-18 2017-07-14 듀얼 사이드 콘택 커패시터를 형성하기 위한 백사이드 실리사이드화의 활용

Country Status (7)

Country Link
US (2) US9847293B1 (https=)
EP (1) EP3501045A1 (https=)
JP (1) JP6921180B2 (https=)
KR (1) KR20190039714A (https=)
CN (1) CN109690788A (https=)
BR (1) BR112019002750B1 (https=)
WO (1) WO2018034756A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9847293B1 (en) 2016-08-18 2017-12-19 Qualcomm Incorporated Utilization of backside silicidation to form dual side contacted capacitor
US12575111B2 (en) * 2022-06-30 2026-03-10 Intel Corporation Back-end-of-line 2D memory cell

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882649A (en) * 1988-03-29 1989-11-21 Texas Instruments Incorporated Nitride/oxide/nitride capacitor dielectric
JP3326267B2 (ja) 1994-03-01 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US5541442A (en) * 1994-08-31 1996-07-30 International Business Machines Corporation Integrated compact capacitor-resistor/inductor configuration
JPH08222701A (ja) * 1995-02-17 1996-08-30 Asahi Chem Ind Co Ltd キャパシタを有する半導体装置およびその製造方法
US6320237B1 (en) 1999-11-08 2001-11-20 International Business Machines Corporation Decoupling capacitor structure
US6984591B1 (en) * 2000-04-20 2006-01-10 International Business Machines Corporation Precursor source mixtures
DE10210044A1 (de) * 2002-03-07 2003-09-18 Philips Intellectual Property Integrierte monolithische SOI-Schaltung mit Kondensator
SE527487C2 (sv) 2004-03-02 2006-03-21 Infineon Technologies Ag En metod för framställning av en kondensator och en monolitiskt integrerad krets innefattande en sådan kondensator
JP2005260163A (ja) 2004-03-15 2005-09-22 Fujitsu Ltd 容量素子及びその製造方法並びに半導体装置及びその製造方法
US20050280087A1 (en) * 2004-06-16 2005-12-22 Cree Microwave, Inc. Laterally diffused MOS transistor having source capacitor and gate shield
US7064043B1 (en) 2004-12-09 2006-06-20 Texas Instruments Incorporated Wafer bonded MOS decoupling capacitor
US20060170044A1 (en) 2005-01-31 2006-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. One-transistor random access memory technology integrated with silicon-on-insulator process
US7345334B2 (en) 2005-04-27 2008-03-18 International Business Machines Corporation Integrated circuit (IC) with high-Q on-chip discrete capacitors
US7709313B2 (en) 2005-07-19 2010-05-04 International Business Machines Corporation High performance capacitors in planar back gates CMOS
US8013342B2 (en) * 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US20090057742A1 (en) 2007-08-30 2009-03-05 Sungjae Lee Cmos varactor
CN101952961B (zh) * 2008-02-25 2013-01-30 飞兆半导体公司 包括集成薄膜电感器的微模块及其制造方法
US8889548B2 (en) * 2008-09-30 2014-11-18 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
JP2011193191A (ja) * 2010-03-15 2011-09-29 Renesas Electronics Corp 半導体集積回路およびそれを内蔵した高周波モジュール
JP5876249B2 (ja) * 2011-08-10 2016-03-02 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US8916421B2 (en) * 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
US20130158378A1 (en) * 2011-09-22 2013-06-20 The Ohio State University Ionic barrier for floating gate in vivo biosensors
US8592241B2 (en) * 2011-09-28 2013-11-26 Freescale Semiconductor, Inc. Method for packaging an electronic device assembly having a capped device interconnect
US8748258B2 (en) 2011-12-12 2014-06-10 International Business Machines Corporation Method and structure for forming on-chip high quality capacitors with ETSOI transistors
US8685790B2 (en) * 2012-02-15 2014-04-01 Freescale Semiconductor, Inc. Semiconductor device package having backside contact and method for manufacturing
JP6216235B2 (ja) * 2013-05-07 2017-10-18 キヤノン株式会社 画像形成装置及びその制御方法とプログラム
US20160043108A1 (en) * 2014-08-07 2016-02-11 Silanna Semiconductor U.S.A., Inc. Semiconductor Structure with Multiple Active Layers in an SOI Wafer
KR20160034200A (ko) * 2014-09-19 2016-03-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
US9257393B1 (en) 2014-09-29 2016-02-09 Freescale Semiconductor Inc. Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof
US9620463B2 (en) * 2015-02-27 2017-04-11 Qualcomm Incorporated Radio-frequency (RF) shielding in fan-out wafer level package (FOWLP)
US9780210B1 (en) * 2016-08-11 2017-10-03 Qualcomm Incorporated Backside semiconductor growth
US9847293B1 (en) 2016-08-18 2017-12-19 Qualcomm Incorporated Utilization of backside silicidation to form dual side contacted capacitor

Also Published As

Publication number Publication date
US20180076137A1 (en) 2018-03-15
US9847293B1 (en) 2017-12-19
BR112019002750B1 (pt) 2023-04-11
WO2018034756A1 (en) 2018-02-22
EP3501045A1 (en) 2019-06-26
CN109690788A (zh) 2019-04-26
BR112019002750A2 (pt) 2019-05-14
US10290579B2 (en) 2019-05-14
JP2019525476A (ja) 2019-09-05
JP6921180B2 (ja) 2021-08-18

Similar Documents

Publication Publication Date Title
CN110088891B (zh) 利用双面处理的逻辑电路块布局
US10431558B2 (en) Method and apparatus for back-biased switch transistors
US9780210B1 (en) Backside semiconductor growth
US10074942B2 (en) Switch device performance improvement through multisided biased shielding
US9812580B1 (en) Deep trench active device with backside body contact
US9917062B1 (en) Self-aligned transistors for dual-side processing
US10043752B2 (en) Substrate contact using dual sided silicidation
US10290579B2 (en) Utilization of backside silicidation to form dual side contacted capacitor
HK40009868A (en) Logic circuit block layouts with dual-sided processing
HK40009868B (en) Logic circuit block layouts with dual-sided processing

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000