KR20190027821A - 재생을 거친 도너 기판의 방법 - Google Patents

재생을 거친 도너 기판의 방법 Download PDF

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Publication number
KR20190027821A
KR20190027821A KR1020197001310A KR20197001310A KR20190027821A KR 20190027821 A KR20190027821 A KR 20190027821A KR 1020197001310 A KR1020197001310 A KR 1020197001310A KR 20197001310 A KR20197001310 A KR 20197001310A KR 20190027821 A KR20190027821 A KR 20190027821A
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KR
South Korea
Prior art keywords
substrate
donor substrate
donor
gan
backing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020197001310A
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English (en)
Korean (ko)
Inventor
프란시스 제이. 헨리
Original Assignee
큐맷, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/643,384 external-priority patent/US20180033609A1/en
Priority claimed from US15/643,370 external-priority patent/US20180019169A1/en
Application filed by 큐맷, 인코포레이티드 filed Critical 큐맷, 인코포레이티드
Priority claimed from PCT/IB2017/054209 external-priority patent/WO2018011731A1/en
Publication of KR20190027821A publication Critical patent/KR20190027821A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H01L33/0079—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
KR1020197001310A 2016-07-12 2017-07-12 재생을 거친 도너 기판의 방법 Withdrawn KR20190027821A (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201662361468P 2016-07-12 2016-07-12
US62/361,468 2016-07-12
US201662367911P 2016-07-28 2016-07-28
US62/367,911 2016-07-28
US15/643,384 US20180033609A1 (en) 2016-07-28 2017-07-06 Removal of non-cleaved/non-transferred material from donor substrate
US15/643,370 2017-07-06
US15/643,384 2017-07-06
US15/643,370 US20180019169A1 (en) 2016-07-12 2017-07-06 Backing substrate stabilizing donor substrate for implant or reclamation
PCT/IB2017/054209 WO2018011731A1 (en) 2016-07-12 2017-07-12 Method of a donor substrate undergoing reclamation

Publications (1)

Publication Number Publication Date
KR20190027821A true KR20190027821A (ko) 2019-03-15

Family

ID=65658530

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197001310A Withdrawn KR20190027821A (ko) 2016-07-12 2017-07-12 재생을 거친 도너 기판의 방법

Country Status (4)

Country Link
EP (1) EP3485505A1 (enExample)
JP (1) JP2019527477A (enExample)
KR (1) KR20190027821A (enExample)
CN (1) CN109478493A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230116016A (ko) * 2021-02-04 2023-08-03 미쓰비시덴키 가부시키가이샤 반도체 기판의 제조 방법 및 반도체 장치의 제조 방법

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110190163B (zh) 2019-05-24 2020-04-28 康佳集团股份有限公司 图形化衬底、外延片、制作方法、存储介质及led芯片
CN115803851B (zh) * 2021-01-21 2023-06-30 信越工程株式会社 工件分离装置及工件分离方法
FR3120159B1 (fr) * 2021-02-23 2023-06-23 Soitec Silicon On Insulator Procédé de préparation du résidu d’un substrat donneur ayant subi un prélèvement d’une couche par délamination
JP7484773B2 (ja) * 2021-03-04 2024-05-16 信越半導体株式会社 紫外線発光素子用エピタキシャルウェーハの製造方法、紫外線発光素子用基板の製造方法及び紫外線発光素子用エピタキシャルウェーハ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2834123B1 (fr) * 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
JP4519199B2 (ja) * 2007-09-03 2010-08-04 パナソニック株式会社 ウエハ再生方法およびウエハ再生装置
SG159484A1 (en) * 2008-09-05 2010-03-30 Semiconductor Energy Lab Method of manufacturing soi substrate
US8679942B2 (en) * 2008-11-26 2014-03-25 Soitec Strain engineered composite semiconductor substrates and methods of forming same
JP2014157979A (ja) * 2013-02-18 2014-08-28 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板およびその製造方法、積層ｉｉｉ族窒化物複合基板、ならびにｉｉｉ族窒化物半導体デバイスおよびその製造方法
WO2016007582A1 (en) * 2014-07-11 2016-01-14 Gtat Corporation Support substrate for ion beam exfoliation of a crystalline lamina

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230116016A (ko) * 2021-02-04 2023-08-03 미쓰비시덴키 가부시키가이샤 반도체 기판의 제조 방법 및 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
EP3485505A1 (en) 2019-05-22
CN109478493A (zh) 2019-03-15
JP2019527477A (ja) 2019-09-26

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Date Code Title Description
PA0105 International application

Patent event date: 20190114

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination