KR20170044595A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR20170044595A
KR20170044595A KR1020160132691A KR20160132691A KR20170044595A KR 20170044595 A KR20170044595 A KR 20170044595A KR 1020160132691 A KR1020160132691 A KR 1020160132691A KR 20160132691 A KR20160132691 A KR 20160132691A KR 20170044595 A KR20170044595 A KR 20170044595A
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KR
South Korea
Prior art keywords
transistor
gate
semiconductor
data
wiring
Prior art date
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Ceased
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KR1020160132691A
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English (en)
Korean (ko)
Inventor
다카유키 이케다
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Publication of KR20170044595A publication Critical patent/KR20170044595A/ko
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    • H01L27/0826—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H01L21/8238—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H01L27/092—
    • H01L29/517—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020160132691A 2015-10-15 2016-10-13 반도체 장치 Ceased KR20170044595A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2015-203976 2015-10-15
JP2015203976 2015-10-15

Publications (1)

Publication Number Publication Date
KR20170044595A true KR20170044595A (ko) 2017-04-25

Family

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Family Applications (1)

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KR1020160132691A Ceased KR20170044595A (ko) 2015-10-15 2016-10-13 반도체 장치

Country Status (3)

Country Link
US (1) US10079231B2 (enExample)
JP (1) JP6864456B2 (enExample)
KR (1) KR20170044595A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11101386B2 (en) 2017-08-04 2021-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018203175A1 (ja) * 2017-05-03 2018-11-08 株式会社半導体エネルギー研究所 半導体装置
CN109427910B (zh) * 2017-08-31 2021-11-23 昆山国显光电有限公司 薄膜晶体管器件及其制作方法
TWI852333B (zh) 2017-12-07 2024-08-11 日商半導體能源研究所股份有限公司 半導體裝置以及半導體裝置的製造方法
WO2019162807A1 (ja) 2018-02-23 2019-08-29 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2019207429A1 (ja) 2018-04-27 2019-10-31 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
CN112352318A (zh) * 2018-07-06 2021-02-09 株式会社半导体能源研究所 半导体装置以及半导体装置的制造方法
JP7190729B2 (ja) 2018-08-31 2022-12-16 三国電子有限会社 キャリア注入量制御電極を有する有機エレクトロルミネセンス素子
JP7246681B2 (ja) 2018-09-26 2023-03-28 三国電子有限会社 トランジスタ及びトランジスタの製造方法、並びにトランジスタを含む表示装置
CN109671454B (zh) * 2018-11-16 2021-05-14 华南理工大学 一种差分逻辑存储器行列选择电路和芯片
US10978563B2 (en) * 2018-12-21 2021-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
WO2020208458A1 (ja) 2019-04-12 2020-10-15 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JPWO2021105828A1 (enExample) 2019-11-29 2021-06-03
KR20220116481A (ko) 2019-12-13 2022-08-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 표시 장치, 및 전자 기기
JP7444436B2 (ja) * 2020-02-05 2024-03-06 三国電子有限会社 液晶表示装置
US20230255038A1 (en) 2020-10-29 2023-08-10 The University Of Tokyo Semiconductor Device and Method of Manufacturing Same
US11699391B2 (en) 2021-05-13 2023-07-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display apparatus, and electronic device
EP4383574A4 (en) * 2021-10-09 2024-09-25 Huawei Technologies Co., Ltd. LOGICAL GATE CIRCUIT, LATCH AND TRIGGER

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3232843C2 (de) * 1981-09-03 1986-07-03 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa MOS-Logikschaltung
JPS61264752A (ja) * 1985-05-20 1986-11-22 Hitachi Ltd 電界効果型半導体装置
JPH09162408A (ja) * 1995-12-06 1997-06-20 Toshiba Corp 半導体集積回路装置
JPH0993118A (ja) 1995-09-22 1997-04-04 Kawasaki Steel Corp パストランジスタ論理回路
JPH09307006A (ja) 1996-05-16 1997-11-28 Oki Electric Ind Co Ltd 半導体集積回路装置
JP3696501B2 (ja) * 2000-12-08 2005-09-21 シャープ株式会社 半導体集積回路
US7345511B2 (en) 2002-08-29 2008-03-18 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
JP4257971B2 (ja) * 2003-03-27 2009-04-30 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタのゲート信号印加方法
US7898297B2 (en) * 2005-01-04 2011-03-01 Semi Solution, Llc Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
WO2006087698A2 (en) 2005-02-16 2006-08-24 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
US7382162B2 (en) * 2005-07-14 2008-06-03 International Business Machines Corporation High-density logic techniques with reduced-stack multi-gate field effect transistors
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
JP5078246B2 (ja) 2005-09-29 2012-11-21 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
US7592841B2 (en) * 2006-05-11 2009-09-22 Dsm Solutions, Inc. Circuit configurations having four terminal JFET devices
EP2515337B1 (en) * 2008-12-24 2016-02-24 Semiconductor Energy Laboratory Co., Ltd. Driver circuit and semiconductor device
JP2011014724A (ja) * 2009-07-02 2011-01-20 Seiko Epson Corp 半導体装置、半導体装置の製造方法、電子機器および電子機器の製造方法
WO2011034012A1 (en) * 2009-09-16 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, light emitting device, semiconductor device, and electronic device
KR101669476B1 (ko) * 2009-10-30 2016-10-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리 회로 및 반도체 장치
FR2964794A1 (fr) * 2010-09-14 2012-03-16 St Microelectronics Sa Circuit de polarisation dynamique du substrat d'un transistor
JP2013084333A (ja) * 2011-09-28 2013-05-09 Semiconductor Energy Lab Co Ltd シフトレジスタ回路
US9461126B2 (en) * 2013-09-13 2016-10-04 Semiconductor Energy Laboratory Co., Ltd. Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11101386B2 (en) 2017-08-04 2021-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JP6864456B2 (ja) 2021-04-28
JP2017076789A (ja) 2017-04-20
US20170110453A1 (en) 2017-04-20
US10079231B2 (en) 2018-09-18

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