KR20170002398A - 저 면적 디지털 soc를 위한 적응형 표준 셀 아키텍처 및 레이아웃 기술들 - Google Patents

저 면적 디지털 soc를 위한 적응형 표준 셀 아키텍처 및 레이아웃 기술들 Download PDF

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Publication number
KR20170002398A
KR20170002398A KR1020167030392A KR20167030392A KR20170002398A KR 20170002398 A KR20170002398 A KR 20170002398A KR 1020167030392 A KR1020167030392 A KR 1020167030392A KR 20167030392 A KR20167030392 A KR 20167030392A KR 20170002398 A KR20170002398 A KR 20170002398A
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KR
South Korea
Prior art keywords
power rail
metal
layer
transistor devices
layer interconnect
Prior art date
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KR1020167030392A
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English (en)
Korean (ko)
Inventor
제이 마드후카르 샤
카메쉬 메디세티
비제야라크쉬미 랑안나
아니메쉬 다타
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퀄컴 인코포레이티드
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Publication of KR20170002398A publication Critical patent/KR20170002398A/ko
Withdrawn legal-status Critical Current

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    • H01L27/0207—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H01L27/11807—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines
    • H01L2027/11881—
    • H10W20/427—

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
KR1020167030392A 2014-05-01 2015-03-16 저 면적 디지털 soc를 위한 적응형 표준 셀 아키텍처 및 레이아웃 기술들 Withdrawn KR20170002398A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/267,888 US9070552B1 (en) 2014-05-01 2014-05-01 Adaptive standard cell architecture and layout techniques for low area digital SoC
US14/267,888 2014-05-01
PCT/US2015/020730 WO2015167679A1 (en) 2014-05-01 2015-03-16 Adaptive standard cell architecture and layout techniques for low area digital soc

Publications (1)

Publication Number Publication Date
KR20170002398A true KR20170002398A (ko) 2017-01-06

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ID=53268859

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167030392A Withdrawn KR20170002398A (ko) 2014-05-01 2015-03-16 저 면적 디지털 soc를 위한 적응형 표준 셀 아키텍처 및 레이아웃 기술들

Country Status (7)

Country Link
US (1) US9070552B1 (enExample)
EP (1) EP3138129A1 (enExample)
JP (1) JP2017517143A (enExample)
KR (1) KR20170002398A (enExample)
CN (1) CN106165097A (enExample)
BR (1) BR112016025414A2 (enExample)
WO (1) WO2015167679A1 (enExample)

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KR20160136715A (ko) * 2015-05-20 2016-11-30 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9935100B2 (en) 2015-11-09 2018-04-03 Qualcomm Incorporated Power rail inbound middle of line (MOL) routing
KR20170059364A (ko) * 2015-11-19 2017-05-30 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
US9634026B1 (en) * 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
US10090244B2 (en) 2016-07-27 2018-10-02 Qualcomm Incorporated Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
US10605859B2 (en) * 2016-09-14 2020-03-31 Qualcomm Incorporated Visible alignment markers/landmarks for CAD-to-silicon backside image alignment
KR102678555B1 (ko) 2016-10-05 2024-06-26 삼성전자주식회사 변형 셀을 포함하는 집적 회로 및 그 설계 방법
US10236886B2 (en) * 2016-12-28 2019-03-19 Qualcomm Incorporated Multiple via structure for high performance standard cells
US10811357B2 (en) 2017-04-11 2020-10-20 Samsung Electronics Co., Ltd. Standard cell and an integrated circuit including the same
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
US10692808B2 (en) 2017-09-18 2020-06-23 Qualcomm Incorporated High performance cell design in a technology with high density metal routing
US10867102B2 (en) * 2018-06-28 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Inverted pitch IC structure, layout method, and system
US11201148B2 (en) * 2018-10-29 2021-12-14 Tokyo Electron Limited Architecture for monolithic 3D integration of semiconductor devices
US11710733B2 (en) * 2020-03-03 2023-07-25 Qualcomm Incorporated Vertical power grid standard cell architecture
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
US11929325B2 (en) * 2021-08-18 2024-03-12 Qualcomm Incorporated Mixed pitch track pattern
US20250336824A1 (en) * 2024-04-26 2025-10-30 Samsung Electronics Co., Ltd. Semiconductor device

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JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
JPH06120224A (ja) * 1992-09-30 1994-04-28 Nec Ic Microcomput Syst Ltd 半導体集積回路
US6502231B1 (en) 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
JP2006196872A (ja) * 2004-12-17 2006-07-27 Matsushita Electric Ind Co Ltd 標準セル、標準セルライブラリ、半導体装置、及びその配置方法
JP2007066974A (ja) * 2005-08-29 2007-03-15 Matsushita Electric Ind Co Ltd 半導体集積回路および半導体集積回路のレイアウト方法
US7989849B2 (en) 2006-11-15 2011-08-02 Synopsys, Inc. Apparatuses and methods for efficient power rail structures for cell libraries
TWI376615B (en) * 2008-01-30 2012-11-11 Realtek Semiconductor Corp Power mesh managing method utilized in an integrated circuit
KR101394145B1 (ko) * 2008-02-26 2014-05-16 삼성전자주식회사 스탠다드 셀 라이브러리 및 집적 회로
JP5552775B2 (ja) * 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
US8421205B2 (en) * 2010-05-06 2013-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Power layout for integrated circuits
US8742464B2 (en) * 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US8756550B2 (en) 2011-09-19 2014-06-17 Texas Instruments Incorporated Method to ensure double patterning technology compliance in standard cells
US8694945B2 (en) 2011-12-20 2014-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Automatic place and route method for electromigration tolerant power distribution
WO2013161249A1 (ja) * 2012-04-24 2013-10-31 パナソニック株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180106826A (ko) * 2017-03-20 2018-10-01 삼성전자주식회사 표준 셀 블록용 파워 레일

Also Published As

Publication number Publication date
BR112016025414A2 (pt) 2017-08-15
CN106165097A (zh) 2016-11-23
US9070552B1 (en) 2015-06-30
WO2015167679A1 (en) 2015-11-05
EP3138129A1 (en) 2017-03-08
JP2017517143A (ja) 2017-06-22

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