KR20160022350A - 피드백 루프 내에 듀티 사이클 조정부를 갖는 주파수 분주기 - Google Patents

피드백 루프 내에 듀티 사이클 조정부를 갖는 주파수 분주기

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Publication number
KR20160022350A
KR20160022350A KR1020167001242A KR20167001242A KR20160022350A KR 20160022350 A KR20160022350 A KR 20160022350A KR 1020167001242 A KR1020167001242 A KR 1020167001242A KR 20167001242 A KR20167001242 A KR 20167001242A KR 20160022350 A KR20160022350 A KR 20160022350A
Authority
KR
South Korea
Prior art keywords
duty cycle
signal
frequency
latch
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167001242A
Other languages
English (en)
Korean (ko)
Inventor
우-흐신 첸
스리람고팔 스리드하라
리 리우
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160022350A publication Critical patent/KR20160022350A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
KR1020167001242A 2013-06-25 2014-06-18 피드백 루프 내에 듀티 사이클 조정부를 갖는 주파수 분주기 Withdrawn KR20160022350A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/926,631 US9379722B2 (en) 2013-06-25 2013-06-25 Frequency divider with duty cycle adjustment within feedback loop
US13/926,631 2013-06-25
PCT/US2014/042920 WO2014209715A1 (en) 2013-06-25 2014-06-18 Frequency divider with duty cycle adjustment within feedback loop

Publications (1)

Publication Number Publication Date
KR20160022350A true KR20160022350A (ko) 2016-02-29

Family

ID=51134456

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167001242A Withdrawn KR20160022350A (ko) 2013-06-25 2014-06-18 피드백 루프 내에 듀티 사이클 조정부를 갖는 주파수 분주기

Country Status (6)

Country Link
US (1) US9379722B2 (enExample)
EP (1) EP3014769A1 (enExample)
JP (1) JP2016525301A (enExample)
KR (1) KR20160022350A (enExample)
CN (1) CN105324938B (enExample)
WO (1) WO2014209715A1 (enExample)

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US9473120B1 (en) * 2015-05-18 2016-10-18 Qualcomm Incorporated High-speed AC-coupled inverter-based buffer with replica biasing
US9712113B2 (en) * 2015-12-01 2017-07-18 Analog Devices Global Local oscillator paths
US9755678B2 (en) 2015-12-01 2017-09-05 Analog Devices Global Low noise transconductance amplifiers
JP6985579B2 (ja) * 2016-07-27 2021-12-22 株式会社ソシオネクスト 分周補正回路、受信回路及び集積回路
CN106685412B8 (zh) * 2016-12-06 2020-01-10 浙江大学 分频器、分频器系统及分频处理方法
CN106685419B (zh) * 2016-12-20 2019-06-07 武汉邮电科学研究院 高精度的宽带分频器
US10148257B1 (en) * 2018-04-19 2018-12-04 Realtek Semiconductor Corp. Method and apparatus for generating twenty-five percent duty cycle clock
US11201611B2 (en) * 2018-12-12 2021-12-14 Intel Corporation Duty cycle control circuitry for input/output (I/O) margin control
US10979036B1 (en) * 2019-06-28 2021-04-13 Dialog Semiconductor B.V. Divider circuit
CN111257628B (zh) * 2020-03-05 2022-05-06 成都飞机工业（集团）有限责任公司 一种交流信号转换为脉冲信号的抗干扰方法

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US3805192A (en) 1972-08-09 1974-04-16 Electronic Communications Frequency modulator-variable frequency generator
JP2539667Y2 (ja) * 1988-06-15 1997-06-25 ソニー株式会社 デューティ可変回路
US6028491A (en) * 1998-04-29 2000-02-22 Atmel Corporation Crystal oscillator with controlled duty cycle
JP3745123B2 (ja) 1998-08-24 2006-02-15 三菱電機株式会社 デューティ比補正回路及びクロック生成回路
US6356129B1 (en) 1999-10-12 2002-03-12 Teradyne, Inc. Low jitter phase-locked loop with duty-cycle control
GB2356301B (en) * 1999-11-10 2003-09-10 Fujitsu Ltd Data multiplexing in mixed-signal circuitry
US7444534B2 (en) 2006-01-25 2008-10-28 International Business Machines Corporation Method and apparatus for dividing a digital signal by X.5 in an information handling system
US7330061B2 (en) * 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal
US7705647B2 (en) 2006-06-14 2010-04-27 Qualcomm Incorporated Duty cycle correction circuit
JP2008011132A (ja) * 2006-06-29 2008-01-17 Nec Electronics Corp ９０度移相器
US8045674B2 (en) 2006-12-06 2011-10-25 Broadcom Corporation Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL
US20100134154A1 (en) * 2007-04-02 2010-06-03 Xin He Odd number frequency dividing circuit
EP2056459B1 (en) 2007-10-16 2012-04-18 austriamicrosystems AG Frequency divider and method for frequency division
US7944262B2 (en) * 2008-05-21 2011-05-17 Elpida Memory, Inc. Duty correction circuit
US7956696B2 (en) 2008-09-19 2011-06-07 Altera Corporation Techniques for generating fractional clock signals
US7839195B1 (en) 2009-06-03 2010-11-23 Honeywell International Inc. Automatic control of clock duty cycle
CN101626237B (zh) * 2009-07-29 2012-05-23 钰创科技股份有限公司 具宽频率锁频范围与避免锁相错误的延迟锁相回路电路
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US8779810B2 (en) 2011-07-15 2014-07-15 Qualcomm Incorporated Dynamic divide by 2 with 25% duty cycle output waveforms
US8643408B2 (en) 2012-01-20 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Flip-flop circuit, frequency divider and frequency dividing method
TWI482435B (zh) * 2012-05-25 2015-04-21 Global Unichip Corp 工作週期校正電路

Also Published As

Publication number Publication date
JP2016525301A (ja) 2016-08-22
WO2014209715A1 (en) 2014-12-31
EP3014769A1 (en) 2016-05-04
CN105324938B (zh) 2018-10-26
US9379722B2 (en) 2016-06-28
US20140375363A1 (en) 2014-12-25
CN105324938A (zh) 2016-02-10

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20160115

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid