KR20150079250A - Liquid crystal display device and method of driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof. In particular, the invention provides a liquid crystal display device capable of controlling an output of a common-mode input voltage transmitted from a common voltage generation unit based on a power signal and a driving voltage transmitted from an external system, and a controlling method thereof. To this end, the liquid crystal display device of the present invention comprises: a panel having a pixel formed in each intersection of data lines and gate lines and having a common electrode; a common voltage generation unit for generating a common-mode input voltage, which is supplied to the common electrode, by using a driving voltage generated through an input voltage transmitted from an external system; a reset unit for generating all high signals for controlling a gate driver by a power signal transmitted from the external system; and a common voltage switching unit for controlling an output of the common-mode input voltage transmitted from the common voltage generation unit by using the all high signals outputted from the reset unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a liquid crystal display device and a driving method thereof using a common voltage VCOM.

Flat panel display devices (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Examples of the flat panel display include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED). Recently, Electrophoretic display devices (EPD) are also widely used.

Among flat panel display devices (hereinafter, simply referred to as 'display devices'), a liquid crystal display device (LCD) is an apparatus for displaying an image using the optical anisotropy of liquid crystal, and has advantages of thinness, small size, low power consumption, Have.

FIG. 1 is a schematic view illustrating a configuration of a conventional liquid crystal display device, and FIG. 2 is a waveform diagram of a power supply applied to a conventional liquid crystal display device. 2, an input voltage VIN is a voltage supplied to a terminal equipped with a liquid crystal display device, and a driving voltage VDD is a voltage generated in the liquid crystal display device using the input voltage VIN .

1, a conventional liquid crystal display includes a panel 10 for outputting an image, a data driver 30 for supplying data voltages to the data lines DL1 to DLd formed on the panel, A gate driver 20 for supplying a scan signal to the gate lines GL1 to GLg formed on the panel, a timing controller 40 for controlling the data driver 20 and the data driver, A common voltage generator 50 for supplying a common voltage to a common electrode formed in the gate driver 20 and an operation for turning off the operation of the gate driver 20 when a power off signal POS is received from an external system And a reset section 60 for transmitting an all-high signal (AHS) to the gate driver 20.

In the panel 10, pixels are formed for each intersection region of the data lines and the gate lines. Wherein the pixel is formed with a switching transistor connected to the gate line, the switching transistor being turned on by a scan pulse transmitted from the gate driver to supply a data voltage supplied through the data line to the pixel, And supplies it to the pixel electrode.

The switching transistor may be an a-Si TFT, a poly-Si TFT, an oxide TFT, an organic TFT, or the like as a thin film transistor (TFT). The oxide TFT has a low threshold voltage (Vth), and in the oxide TFT, a leakage current hardly occurs in an off state. That is, there is no natural discharge due to a leakage current in the oxide TFT.

Therefore, when the power of the conventional liquid crystal display device in which the oxide TFT is used is turned off, the remaining charges that are not discharged are accumulated, which may cause a problem in the liquid crystal display device.

For example, since the oxide TFT has a low leakage current characteristic, it is necessary to discharge all residual DCs during power-off to secure characteristics such as afterimage, but a method of discharging all of the residual DCs is provided I can not.

2, the data voltages (Positive and Negative) output from the data driver and the common voltage VCOM generated by the common voltage generator 50 are supplied to the power source It is dependent on the natural discharge of the driving voltage VDD. As a result, unwanted data charging can occur at power-off. In other words, unwanted pixel charging is continued for several tens of ms during which the gate driver 20 is discharged by the all-high signal (AHS). Accordingly, when the liquid crystal display device is powered off, .

The phenomenon that the data voltages depend on the discharge of the driving voltage VDD is solved by a method of connecting the data lines to the ground at the time of power-off.

However, in the conventional liquid crystal display device, the phenomenon that the common voltage depends on the discharge of the driving voltage (VDD) is not solved.

That is, when the input voltage VIN is off, the driving voltage VDD also turns off along the input voltage VIN. When the driving voltage VDD is turned off, the data voltages Positive and Negative generated by the driving voltage VDD and the common voltage VCOM are also turned off along the driving voltage VDD. In this case, the driving voltage VDD is gradually reduced along the input voltage VIN as shown in FIG. Therefore, since the common voltage is supplied to the panel while the driving voltage VDD is turned off, an undesired image can be output from the panel at the time of power-off.

1, the common voltage generator 50 generates the common voltage VCOM by using the driving voltage VDD. Therefore, when the common voltage VCOM is generated, Is discharged at the same level as the driving voltage VDD. Therefore, the discharge of the common voltage VCOM is difficult to control individually.

According to an aspect of the present invention, there is provided a liquid crystal display device capable of controlling an output of an input common voltage transmitted from a common voltage generator according to a power signal and a driving voltage transmitted from an external system, And to provide a driving method.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a panel having pixels formed in intersecting regions of data lines and gate lines, A common voltage generator for generating an input common voltage to be supplied to the common electrode by using a driving voltage generated by an input voltage transmitted from an external system; A reset unit for generating an all-high signal for controlling the gate driver according to a power signal transmitted from the external system; And a common voltage switching unit for controlling the output of the input common voltage transmitted from the common voltage generating unit using the all-high signal outputted from the reset unit.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, including: driving an input common voltage to be supplied to a common electrode formed on a panel using a driving voltage generated by an input voltage transmitted from an external system; ; Generating an all-high signal for controlling the gate driver according to a power signal transmitted from the external system; And controlling the output of the input common voltage using the all-high signal and the driving voltage.

According to the present invention, when the external system is powered off, the common voltage quickly changes to the ground level, thereby preventing the abnormal screen from being output through the panel while the external system is powered off.

1 is an exemplary view schematically showing a configuration of a conventional liquid crystal display device.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
3 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
FIG. 4 is a waveform diagram of a power source applied to a liquid crystal display device according to an embodiment of the present invention. FIG.
FIG. 5 is a schematic view illustrating a configuration of a common voltage switching unit applied to a liquid crystal display device according to the present invention; FIG.
6 is a diagram illustrating a specific configuration of a common voltage switching unit applied to a liquid crystal display device according to the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an organic light emitting display according to an embodiment of the present invention.

3, a pixel (not shown) is formed for each intersection region of the data lines DL1 to DLd and the gate lines GL1 to GLg, An input common voltage Vcom 'to be supplied to the common electrode is generated using a driving voltage VDD generated by an input voltage transmitted from an external system (not shown) A reset unit 600 for generating an all-high signal AHS for controlling the gate driver 200 according to a power signal POS transmitted from the external system, A common voltage switching unit 700 for controlling the output of the input common voltage Vcom 'transmitted from the common voltage generator 500 using the all-high signal AHS output from the reset unit 600, .

First, in the panel 100, the first substrate and the second substrate are bonded together through a laminating process. A liquid crystal layer is formed between the first substrate and the second substrate.

The first substrate and the second substrate may be made of glass, plastic, metal, or the like. The liquid crystal layer is filled with a liquid crystal.

In the display region 110 of the first substrate, a plurality of data lines DL1 to DLd and a plurality of gate lines GL1 to GLg intersecting the data lines are formed. A thin film transistor (TFT) and a pixel electrode for filling a data voltage with the pixel are formed in the pixel formed at each intersection region of the data lines and the gate lines. That is, the pixels are arranged in a matrix by the intersection structure of the data lines DL1 to DLd and the gate lines GL1 to GLg.

The thin film transistor (TFT) supplies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line. The transmittance of light is adjusted by driving the liquid crystal in which the pixel electrode is located in contact with the common electrode in response to the data voltage.

The thin film transistor (TFT) may be an a-Si TFT, a poly-Si TFT, an oxide TFT, an organic TFT, or the like. Particularly, as the thin film transistor (TFT) used in the present invention, the above-mentioned oxide TFT can be used.

The oxide TFT has a feature that the threshold voltage (Vth) is low. Since the threshold voltage is low, leakage current rarely occurs in the off state in the oxide TFT.

The panel 100 may be driven in an IPS mode or a TN mode. In the panel 100 driven in the IPS mode, a pixel electrode and the common electrode are disposed on a lower substrate constituting the panel 100, that is, on the first substrate, and the pixel electrode and the common electrode The arrangement of the liquid crystals is controlled by the transverse electric field between them.

In the TN mode, the pixel electrode is formed on the first substrate, and the common electrode is formed on the second substrate.

The second substrate of the panel 100 may be a color filter substrate. A black matrix (BM), a color filter, and the like are formed on the second substrate.

The timing controller 400 generates a gate control signal GCS for controlling the gate driver 200 using a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal CLK supplied from an external system (not shown) And a data control signal DCS for controlling the data driver 300.

The external system is mounted on a terminal to which the liquid crystal display device according to the present invention is attached, and performs the function of driving the terminal and the liquid crystal display device. The external system may be, for example, a scaler.

From the external system, the vertical synchronizing signal, the horizontal synchronizing signal, the clock signal, and the like and the input image data as described above are input to the timing controller 400.

The gate control signal GCS generated in the timing controller 400 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal VST, GCLK).

A source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL are input to the data control signals DCS generated by the timing controller 400 .

The timing controller 400 samples the input image data input from the external system, rearranges the input image data, and supplies the rearranged digital image data to the data driver 300.

That is, the timing controller 400 rearranges the input image data supplied from the external system to transmit the rearranged digital image data to the data driver 300, and outputs the clock signal CLK supplied from the external system, And the gate driver 200 are controlled using the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync and the data enable signal DE (the signals are simply referred to as a timing signal TS) And a data control signal DCS for controlling the data driver 300 and transmits the generated gate control signal GCS and the data control signal DCS to the gate driver 200 and the data driver 300.

In order to perform the functions as described above, the timing controller 400 includes a receiver for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals as described above, A data arrangement unit for rearranging the input image data and outputting rearranged image data, and an output unit for outputting the control signals and the image data.

As described above, the timing controller 400 rearranges the input image data input from the external system according to the structure and characteristics of the panel 100, and outputs the rearranged image data to the data driver 300 send. Such a function can be executed in the data arrangement section.

The timing controller 400 may use the timing signals transmitted from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, And a gate control signal (GCS) for controlling the gate driver (200). This function can be executed in the control signal generation unit.

Next, the data driver 300 converts the image data inputted from the timing controller 400 into an analog data voltage, and supplies a data voltage of one horizontal line in each horizontal period in which the gate pulse is supplied to the gate line To the data lines.

That is, the data driver 300 converts the image data into data voltages using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the data voltages to the data lines.

The data driver 300 generates a sampling signal by shifting the source start pulse transmitted from the timing controller 400 according to the source shift clock. The data driver 300 latches the image data according to the sampling signal, changes the data voltage to the data voltage, and outputs the data voltage in units of horizontal lines in response to the source output enable signal. .

For this, the data driver 300 may include a shift register unit, a latch unit, a digital-analog converter, and an output buffer.

When the external system and the liquid crystal display device are powered off, the data driver 300 may be configured to perform a discharging function.

That is, when the external system and the liquid crystal display device are turned off, all of the charges remaining in the data driver 300 and the pixels must be discharged. Again, when the external system and the liquid crystal display device are powered on , The data driver 300 and the pixels can be driven normally more quickly.

To this end, the data driver 300 may be formed such that the data lines are connected to the ground when the external system and the liquid crystal display device are powered off.

That is, as mentioned in the related art, since the data voltages output from the data driver and the common voltage generated in the common voltage generator are dependent on the natural discharge of the driving voltage (VDD) at the time of power-off , Undesired data charging may occur at power-off. In order to prevent this, the data driver 300 may be driven such that the data lines are connected to the ground, as mentioned above. However, the above-described functions of the data driver 300 are outside the scope of the present invention, so that a detailed description thereof will be omitted.

According to the present invention, by preventing the common voltage from being supplied to the common electrode when the external system and the liquid crystal display device are powered off, a phenomenon in which an unwanted image is output from the panel (100) .

The gate driver 200 sequentially applies scan pulses to the gate lines GL1 to GLg of the panel 100 in response to the gate control signal GCS input from the timing controller 400 Supply. Accordingly, the switching transistors formed in each pixel of the corresponding horizontal line to which the scan pulse is input are turned on, and light may be output to each pixel.

That is, the gate driver 200 shifts a gate start pulse (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC) On voltage to scan lines GL1 to GLg. In addition, the gate driver 200 supplies a gate-off voltage to the gate lines GL1 to GLn during the remaining period during which the scan pulse is not supplied.

The gate driver 200 may be formed independently from the panel 100 and may be electrically connected to the panel 100 in various ways, (Gate In Panel: GIP) method. In this case, the gate control signal for controlling the gate driver 200 may be a start signal VST and a gate clock GCLK.

When the external system and the liquid crystal display device are powered off, the gate driver 200 may perform a discharging function by the all-high signal AHS transmitted from the reset unit 600. [

That is, when the external system and the liquid crystal display device are powered off, all the electric charges remaining in the gate driver 200 must be discharged. Again, when the external system and the liquid crystal display device are powered on, The driver 200 can be normally driven more quickly.

To this end, the all-high signal (AHS) is supplied to the gate driver 200. The all-high signal (AHS) may have a low level according to a power signal (POS) transmitted from the external system, or may have a high level.

In the above description, the data driver 300, the gate driver 200 and the timing controller 400 are independently configured. However, at least one of the data driver 300 and the gate driver 200 May be integrally formed with the timing controller 400. FIG.

Next, the common voltage generator 500 generates an input common voltage Vcom 'to be supplied to the common electrode using the driving voltage VDD generated by the input voltage VIN transmitted from the external system .

Here, the input voltage VIN is a voltage supplied from an external power supply unit to a terminal in which the liquid crystal display device is mounted. That is, when the terminal is connected to the external power supply unit, the input voltage VIN is supplied to the terminal.

The driving voltage VDD is generated using the input voltage VIN and is a voltage used in the liquid crystal display device. That is, the input voltage VIN is transmitted to the liquid crystal display through the terminal, and the liquid crystal display converts the input voltage VIN into the driving voltage VDD.

The driving voltage VDD may be used to generate power to be supplied to the data driver 300 and the gate driver 200. [

In particular, the driving voltage VDD may be supplied to the common voltage generator 500 as shown in FIG. In this case, the common voltage generator 500 generates the input common voltage Vcom 'by using the driving voltage VDD Dmf.

The input common voltage Vcom 'is supplied to the common electrode through the common voltage switching unit 700. The input common voltage Vcom 'passing through the common voltage switching unit 700 is referred to as a common voltage Vcom.

The input common voltage Vcom 'may be cut off by the common voltage switching unit 700 and not supplied to the common electrode.

The configuration and the function of the common voltage generator 500 are the same as the configuration and the function of the common voltage generator 500 applied to general liquid crystal display devices, and a detailed description thereof will be omitted.

Next, the reset unit 600 generates an all-high signal (AHS) for controlling the gate driver 200 according to the power signal POS transmitted from the external system (not shown).

The power signal POS may include information that the external system is powered off, or may include information that the external system is powered on.

The all-high signal AHS performs a function of causing the gate driver 200 to perform a discharging function when the external system and the liquid crystal display device are powered off.

When the power signal including information that the external system is powered off is received from the external system, the reset unit 600 outputs the all-high signal AHS having a low level, And outputs the all-high signal AHS having a high level when the power signal POS containing information that the system is powered on is output.

When the external system and the liquid crystal display device are powered off, the gate driver 200 may perform a discharging function by the all-high signal AHS transmitted from the reset unit 600. [

That is, when the all-high signal AHS has a low level, the gate driver 200 performs a discharging function. As the discharge function is performed, the gate driver 200 can be normally driven more quickly when the external system and the liquid crystal display are powered on again.

Lastly, the common voltage switching unit 700 uses the all-high signal AHS output from the reset unit 600 to generate the common voltage Vcom from the common voltage generator 500, &Quot;) < / RTI >

The common voltage switching unit 700 will be described below in detail with reference to FIGS. 4 to 6. FIG.

FIG. 4 is a waveform diagram of a power source applied to a liquid crystal display device according to the present invention, FIG. 5 is an exemplary view schematically showing the configuration of a common voltage switching part applied to a liquid crystal display device according to the present invention, Is an exemplary diagram showing a specific configuration of a common voltage switching unit applied to a liquid crystal display device according to the present invention.

The common voltage switching unit 700 applied to the liquid crystal display according to the present invention supplies the input common voltage VCOM 'to the common electrode when the all-high signal AHS is at a high level, When the all-high signal AHS is low level, the output of the input common voltage VCOM 'is cut off. Therefore, as shown in Fig. 4, in accordance with the all-high signal AHS, the input common voltage VCOM 'can be quickly cut off in a short time such as 10 mu m.

That is, as shown in FIG. 4, the period (10 mu m) during which the all-high signal AHS falls from the high level to the low level is a period during which the input voltage VIN and the driving voltage VDD are high Level to a low level.

5, the common voltage switching unit 700 applied to the liquid crystal display according to the present invention uses the driving voltage VDD and the all-high signal AHS, The input common voltage VCOM 'received from the common electrode 500 can be outputted to the common electrode or blocked.

5, the common voltage switching unit 700 includes a first transistor T1 which is turned on or off by the all-high signal AHS and a second transistor T1 which is turned on or off by the all- And a second transistor T2 that is turned off when the first transistor T1 is turned on and turned on by the driving voltage VDD when the first transistor T1 is turned off.

In this case, the input common voltage VCOM 'is output to the common electrode when the second transistor T2 is turned off.

More specifically, the all-high signal AHS has a high level when the external system is powered on, and when the all-high signal has a high level, the first transistor T1 is turned on do. When the first transistor T1 is turned on, the driving voltage VDD is supplied to the first transistor T1. Therefore, the second transistor T2 is turned off. When the second transistor T2 is turned off, the input common voltage VCOM 'is supplied to the common electrode.

The all-high signal AHS has a low level when the external system is powered off and the first transistor T1 is turned off when the all-high signal AHS has a low level. do. When the first transistor T1 is turned off, the driving voltage VDD is supplied to the second transistor T2. As the driving voltage VDD is supplied to the second transistor T2, the second transistor T2 is turned on. As the second transistor T2 is turned on, the input common voltage VCOM 'is supplied to the second transistor T2, so that the input common voltage VCOM' is not output to the common electrode .

That is, the input common voltage VCOM 'may be supplied to the common electrode or may be cut off according to the all-high signal AHS and the driving voltage VDD.

The common voltage switching unit 700 may be configured to include a plurality of option units 710 to 740, as shown in FIG.

That is, the option units 710 to 740 are connected to the first transistor T1, the second transistor T2, the line to which the all-high signal AHS is supplied, the line to which the driving voltage VDD is supplied, And a line to which the input common voltage VCOM 'is supplied to adjust a threshold voltage of the first transistor T1 and the second transistor T2.

Therefore, the options 710 to 740 can be changed into various structures in addition to the structure shown in FIG.

A method of driving a liquid crystal display according to the present invention will now be described. Hereinafter, the same or similar contents as those described above are omitted or briefly described.

The driving method of a liquid crystal display according to the present invention is a method of driving a liquid crystal display using a driving voltage VDD generated by an input voltage transmitted from an external system, Generating an input common voltage VCOM 'to be supplied to an electrode (not shown), controlling the gate driver 200 according to a power signal POS transmitted from the external system by the reset unit 600 (AHS), and the common voltage switching unit 700 controls the output of the input common voltage VCOM 'using the all-high signal AHS and the driving voltage VDD .

Here, when the power signal POS containing information that the external system is powered off is received from the external system, the reset unit 600 outputs the all-high signal AHS having a low level And outputs the all-high signal AHS having a high level when the power signal POS containing information that the external system is powered on is output.

The common voltage generator 500 generates the input common voltage VCOM 'using the same method as the conventional common voltage generator generates the input common voltage VCOM'. The common voltage generator 500 according to the present invention differs from the conventional common voltage generator in that the input common voltage generated by the conventional common voltage generator is directly input to the common electrode, And the input common voltage generated by the common voltage generator 500 is output to the common voltage switching unit 700. That is, the input common voltage generated by the conventional common voltage generator becomes a common voltage that is directly transmitted to the common electrode.

The common voltage switching unit 700 supplies the input common voltage VCOM 'to the common electrode when the all-high signal AHS is at a high level, And blocks the output of the input common voltage VCOM 'when the driving voltage VDD is at a high level.

The present invention described above is briefly summarized as follows.

The present invention is characterized in that the common voltage is discharged in a period of less than 10 占 퐉 in the same manner as the improved data discharge characteristic. Here, the improved data discharge characteristic can be achieved by a method of causing the data lines to be connected to the ground when the external system and the liquid crystal display are powered off, as described above. However, the data discharge characteristic is not within the scope of the present invention. In addition, the data discharge characteristic can be achieved by various methods other than the method described above. In this case, due to the data discharge characteristic, the charges charged in the data line can be discharged within a period of 10 mu m or less.

That is, the present invention is for discharging the common voltage within a period of 10 占 퐉 in the same manner as the data discharge characteristic, thereby forming the common voltage at the ground level.

To this end, in the present invention, the common voltage switching unit 700 is formed. When the external system and the liquid crystal display are powered off, the common voltage switching unit 700 uses the all-high signal AHS, which is a control signal for discharging the gate driver 200, The common voltage VCOM 'is switched so that the common voltage is formed at a ground level within a period of 10 mu m or less.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: Common voltage generator 600:
700: Common voltage switching unit

Claims (10)

A panel in which pixels are formed at intersecting regions of the data lines and the gate lines, and a common electrode is formed;
A common voltage generator for generating an input common voltage to be supplied to the common electrode by using a driving voltage generated by an input voltage transmitted from an external system;
A reset unit for generating an all-high signal for controlling the gate driver according to a power signal transmitted from the external system; And
And a common voltage switching unit for controlling the output of the input common voltage transmitted from the common voltage generating unit using the all-high signal outputted from the reset unit. The method according to claim 1,
Wherein the reset unit comprises:
When the power signal including information that the external system is powered off is received from the external system, outputs the all-high signal having a low level and includes information that the external system is powered on And outputs the all-high signal having a high level when the power signal is received. The method according to claim 1,
Wherein the common voltage switching unit includes:
And supplies the input common voltage to the common electrode when the all-high signal is at a high level and blocks the output of the input common voltage when the all-high signal is at a low level. . The method of claim 3,
The period during which the all-high signal falls from the high level to the low level is shorter than the period during which the driving voltage falls from the high level to the low level. The method according to claim 1,
Wherein the common voltage switching unit includes:
And outputs or blocks the input common voltage received from the common voltage generator to the common electrode using the driving voltage and the all-high signal. The method according to claim 1,
Wherein the common voltage switching unit includes:
A first transistor which is turned on or off by the all-high signal; And
And a second transistor that is turned off when the first transistor is turned on and turned on by the driving voltage when the first transistor is turned off,
Wherein the input common voltage is output to the common electrode when the second transistor is turned off. The method according to claim 6,
Wherein the all-high signal has a high level when the external system is powered on and the first transistor is turned on when the all-high signal has a high level, and when the first transistor is turned on, The transistor is turned off, the input common voltage is supplied to the common electrode,
Wherein the all-high signal has a low level when the external system is powered off and the first transistor is turned off when the all-high signal has a low level, and when the first transistor is turned off, And the second transistor is turned on by the driving voltage so that the output of the input common voltage is cut off. Generating an input common voltage to be supplied to the common electrode formed on the panel using the driving voltage generated by the input voltage transmitted from the external system;
Generating an all-high signal for controlling the gate driver according to a power signal transmitted from the external system; And
And controlling the output of the input common voltage using the all-high signal and the driving voltage. 9. The method of claim 8,
Wherein generating the all-high signal comprises:
When the power signal including information that the external system is powered off is received from the external system, outputs the all-high signal having a low level and includes information that the external system is powered on And outputs the all-high signal having a high level when the power signal is received. 10. The method of claim 9,
Wherein the step of controlling the output of the input common voltage comprises:
Supplying the input common voltage to the common electrode when the all-high signal is at a high level;
And blocking the output of the input common voltage when the all-high signal is at a low level and the driving voltage is at a high level.

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