KR20140137831A - Display Device For Low-speed Driving And Driving Method Of The Same - Google Patents

Abstract

A display device for low-speed driving according to the present invention includes a display panel where gate lines intersect with data lines, and a pixel is formed in intersection parts; a gate driver which supplies a gate pulse to the gate lines; a timing controller which time-divides a first frame into n subframes (n is a positive integer of two or more) and groups the gate lines with n gate groups, controls the operation of the gate driver, disperses the n gate groups to the n subframes and scans them to extend a first gate time required for scanning a gate line to an n horizontal period, generates a switch control signal with a first level in a first period corresponding to (n-1)/n of the first gate time, continues for the first period, and generates the switch control signal with a second level in a second period corresponding to 1/n of the first gate time; and a source driver which allows a common line to which the data lines and a common voltage are supplied for the first period according to the switch control signal of the first level, to be short-circuited, supplies the common voltage to the data lines, and supplies data voltage to the data lines for the second period according to the switch control signal of the second level.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device for low-speed driving and a driving method thereof.

The present invention relates to a display device for low-speed driving and a driving method thereof.

The display device is used for various display devices such as portable information devices, office equipment, computers, and televisions. The display device includes a display panel for displaying an image and a driver for driving the display panel. In the display panel, a plurality of data lines and a plurality of gate lines are formed, and a pixel is formed for each of the intersection areas. The driver includes a source driver for driving the data lines and a gate driver for driving the gate lines.

There are various methods for reducing power consumption in a display device, one of which is a low-speed driving technique. The low speed drive technology refreshes the entire screen of the display device at a frame frequency lower than the input frame frequency. The low-speed driving technique can be implemented through interlace driving as shown in Fig. Interlace driving time-divides one frame into a plurality of sub-frames, and makes gate lines driven in each sub-frame different from each other. That is, the interlaced driving is implemented by the gate lines being distributedly driven in each sub-frame.

For example, when an image is input from the host at an input frame frequency of 60 Hz as shown in FIG. 1, the display device divides one frame into a first sub-frame (SF1) and a second sub-frame (SF2) The odd gate lines G1, G3, G5 and G7 are sequentially scanned in the first sub-frame SF1 and the even-numbered gate lines G2, G4, G6 and G8 are sequentially scanned in the second sub- Thereby realizing a 30 Hz interlace drive. One gate time (indicating the charging time of the pixels arranged on one horizontal line) required to scan one gate line during 30 Hz interlace driving is 2H, which is comparable to 1H, which is one gate time at normal driving of 60 Hz It doubles.

As another example, when an image is input at an input frame frequency of 60 Hz from the host as shown in FIG. 1, the display apparatus displays one frame as a first sub-frame SF1, a second sub-frame SF2, Frame SF3 and the fourth sub-frame SF4 and sequentially scans the fourth gate line G1 and G5 in the first sub-frame SF1 to the (m + The fourth m + 2 gate lines G2 and G6 are sequentially scanned in the second sub-frame SF2 and the fourth m + 3 gate lines G3 and G7 are sequentially scanned. In the fourth sub-frame SF4, By sequentially scanning the 4m + 4 gate lines G4 and G8, 15Hz interlace driving is implemented. One gate time required to scan one gate line during 15Hz interlace driving is 4H, which is four times as large as 1H, which is one gate time at 60Hz normal driving.

In interlaced driving, as the number of subframes is increased, one frame period increases and the frame frequency decreases. As the frame frequency is further reduced at 60 Hz for low-speed driving, the data transition frequency used to supply the data voltage in the source driver decreases. When the data transition frequency is reduced as described above, the accumulation time of the residual DC voltage in the display panel increases, resulting in a DC (direct current) afterimage. When a direct current voltage is applied to the liquid crystal layer of the liquid crystal cell for a long time by low speed driving, ions having negative charges move in the same motion vector direction along the polarity of the electric field applied to the liquid crystal, and ions having positive charge move in the opposite direction , And the amount of accumulation of negatively charged ions and accumulation of positively charged ions increases with time. As a result, ion impurities remaining in the liquid crystal cell are accumulated in the residual direct current voltage on the surface of the alignment film to change the electric characteristics and the tilt angle of the liquid crystal, and as a result, a DC afterimage is generated.

In order to improve the DC after-image described above, attempts have been made to develop a liquid crystal material having a low dielectric constant or to improve an alignment material or an alignment method. However, such a method requires much time and expense to develop materials, and lowering the dielectric constant of the liquid crystal may cause another problem that the driving characteristic of the liquid crystal is deteriorated. Experimental findings indicate that the time of appearance of the DC afterglow due to the polarization and accumulation of ions is accelerated as the impurity ionized in the liquid crystal layer becomes larger and the acceleration factor becomes larger. The acceleration factor is temperature, time, direct current driving of the liquid crystal, and the like. Therefore, the DC residual image appears and becomes worse as the temperature is high or the DC voltage of the same polarity is applied to the liquid crystal layer. Furthermore, the DC after-image can not be solved only by the development of new materials or the improvement of the process because the shapes and degrees of the DC after-images are different even in the panels of the same model manufactured through the same manufacturing line.

Accordingly, it is an object of the present invention to provide a low-speed driving display device and a method of driving the same that can minimize a DC residual image generated in a low-speed driving implementation.

In order to achieve the above object, a display device for low-speed driving according to an embodiment of the present invention includes a display panel in which a plurality of gate lines and a plurality of data lines intersect and pixels are formed at the intersections; A gate driver for supplying a gate pulse to the gate lines; One frame is divided into n sub-frames (n is a positive integer of 2 or more) sub-frames, the gate lines are grouped into n gate groups, and the operation of the gate driver is controlled to control the n gate groups (n-1) / n of the one-gate time, and the gate period is increased to n horizontal periods by scanning one of the gate lines by scattering in n sub- A timing controller generating a control signal at a first level and generating the switch control signal at a second level in a second period that is continuous to the first period and corresponds to 1 / n of the one gate time; And supplying a common voltage to the data lines by shorting a common line supplied with a common voltage to the data lines during the first period according to the switch control signal of the first level, And a source driver for supplying a data voltage to the data lines during the second period according to a signal.

The n horizontal period indicates a value obtained by multiplying one horizontal period defined as a value obtained by dividing one frame period by the number of gate lines by n.

Wherein each of the pixels includes a pixel electrode to which the data voltage is supplied, a common electrode to which the common voltage is supplied, and a liquid crystal layer formed between the pixel electrode and the common electrode; During the first period, the pixel electrode and the common electrode are equipotential by a common voltage.

The source driver includes: a first output channel through which a first polarity data voltage is output; A second output channel through which a second polarity data voltage is output; Wherein the first polarity data voltage is selectively supplied to one of the first data line and the second data line which are adjacent to each other among the data lines, A first switch group for selectively supplying a polarity data voltage to the other one of the first data line and the second data line; And a second switch group which is switched in accordance with the switch control signal of the first level to short-circuit the first data line and the second data line to the common line.

The subframes include alternating odd subframes and even subframes, and a plurality of gate times are allocated to each of the odd subframe and the even subframe.

The first switch group being turned on only in the second period of each of the gate times belonging to each odd subframe to supply the first polarity data voltage to the first data line; A fourth polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each odd subframe and supplies the second polarity data voltage to the second data line; A second polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each of the even sub-frames to supply the first polarity data voltage to the second data line; And a fourth polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each of the even sub-frames to supply the second polarity data voltage to the first data line.

The second switch group being turned on in the first period of each of the gate times belonging to each of the subframes to short the first data line to the common line; And a second 2 < nd > equipotential switch that turns on simultaneously with the 2 < nd > equalization switch in the first period of each of the gate times belonging to each of the subframes and shortens the second data line to the common line. .

The switch control signal is selected as a source output enable signal for controlling the output of the source driver.

In addition, according to an embodiment of the present invention, there is provided a display panel including a display panel in which a plurality of gate lines and a plurality of data lines intersect and pixels are formed at the intersections, a gate driver for supplying gate pulses to the gate lines, (N is a positive integer equal to or larger than 2) sub-frames, and the gate lines are divided into n gate groups Grouping the n gate groups into n sub-frames by controlling the operation of the gate driver to increase the one gate time required to scan one gate line to n horizontal periods; A second period that is continuous to the first period and corresponds to 1 / n of the 1-gate time, in a first period corresponding to (n-1) / n of the 1-gate time, Generating the switch control signal at a second level; Controlling the operation of the source driver according to the first level switch control signal to supply a common voltage to the data lines by shorting common lines supplied with the common voltage with the data lines during the first period ; And controlling the operation of the source driver according to the second level switch control signal to supply the data voltage to the data lines during the second period.

The present invention increases the one-gate time required for scanning one gate line to nH through low-speed driving through the interlace driving technique, supplies the data voltage to the pixel electrodes of the liquid crystal cells only for 1H of one gate time, (N-1) H of one gate time, a common voltage is supplied to the pixel electrodes of the liquid crystal cells to form the equal potential between the pixel electrode and the common electrode, thereby preventing the residual DC voltage from accumulating on the surface of the alignment film, can do.

Brief Description of the Drawings Fig. 1 is a diagram showing a change in frame frequency during interlace driving in contrast to normal driving. Fig.
2 is a diagram showing an example in which the gate time is increased by one in the conventional low-speed driving.
Fig. 3 is a diagram showing another example of increase in one gate time in the conventional low-speed driving. Fig.
4 is a block diagram showing a display device for low-speed driving according to an embodiment of the present invention.
FIG. 5 is a view showing that one frame is time-divided into n sub-frames and the interlaced driving is implemented by dispersively driving the gate lines through each sub-frame.
6 is a waveform diagram for explaining an operation of a source driver for allocating only 1H of the one gate time increased by the interlace drive to the supply of the data voltage and allocating the remaining period to the common voltage supply for equipotential formation.
7 is a diagram illustrating switches connected between an output channel and a data line of a source driver for operation as in FIG.
8 is a view showing a part of a source driver in detail, including the switches in Fig. 7; Fig.
Fig. 9 is a diagram showing the switching states of the switches shown in Fig. 8 within one frame; Fig.
Fig. 10 is a waveform diagram for explaining the operations of Figs. 7 and 8 during the first sub-frame when one frame is divided into 6 sub-frames. Fig.
FIG. 11 is a diagram showing a gate pulse generated in each subframe and a data waveform supplied to data lines in each gate time of each subframe in the case of one frame being time-divided into six subframes; FIG.
Figure 12 shows the effect of the present invention as compared to the prior art.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 12. FIG.

4 is a block diagram showing a display device for low-speed driving according to an embodiment of the present invention. FIG. 5 shows that one frame is time-divided into n subframes and the interlaced driving is implemented by dispersively driving the gate lines through each subframe. 6 shows the operation of the source driver which allocates only 1H of the one gate time increased by the interlace drive to the supply of the data voltage and allocates the remaining period to the common voltage supply for equipotential formation.

5, a low-speed driving display device according to the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) An organic light emitting diode (OLED) display, and an electrophoresis (EPD) display device. In the following embodiments, the display device will be described mainly with respect to the liquid crystal display device, but it should be noted that the display device of the present invention is not limited to the liquid crystal display device.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 15 and the gate lines 16. [

On the lower glass substrate of the liquid crystal display panel 10, a pixel array is formed. The pixel array includes a liquid crystal cell (Clc, pixel) formed at the intersection of the data lines 15 and the gate lines 16, TFTs connected to the pixel electrode 1 of the pixels, A common electrode 2 and a storage capacitor Cst. Each of the liquid crystal cells Clc is connected to a TFT (Thin Film Transistor) and driven by an electric field between the pixel electrode 1 and the common electrode 2. A black matrix, red (R), green (G), and blue (B) color filters are formed on the upper glass substrate of the liquid crystal display panel 10. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS . The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives digital video data RGB of an input image from the host system 14 through a low voltage differential signaling (LVDS) interface method and converts the digital video data RGB of the input video into mini-LVDS And supplies it to the source driver 12 through the interface method. The timing controller 11 arranges the digital video data (RGB) input from the host system 14 in accordance with the layout configuration of the pixel array, and supplies the sorted data to the source driver 12. [

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14, And generates control signals for controlling the operation timings of the driver 12 and the gate driver 13. [ The control signals include a gate timing control signal for controlling the operation timing of the gate driver 13 and a source timing control signal for controlling the operation timing of the source driver 12. [

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to a gate drive IC (integrated circuit) generating a first gate pulse to control the gate drive IC so that a first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the source driver 12. [ The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the source driver 12 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages sequentially output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the source driver 12.

The timing controller 11 controls the operation of the source driver 12 and the gate driver 13 in order to realize low-speed driving through interlace driving. The timing controller 11 outputs digital video data RGB inputted at a frame frequency of 60 Hz in a pixel array of the liquid crystal display panel 10 in accordance with a frame frequency of 60 x 1 / n (n is a positive integer) the gate timing control signal and the source timing control signal are appropriately generated so as to be refreshable.

5, the timing controller 11 time-divides one frame into n (n is a positive integer equal to or greater than 2) subframes and distributes the gate lines 16 through each subframe to implement interlace driving . The timing controller 11 groups the gate lines 16 into n gate groups G_Group # 1 to G_Gn # n and generates n gate groups G_Group # 1 to G # n) to each of the n sub-frames SF1 to SFn in accordance with the driving sequence. 11, the first gate group composed of the (6m + 1) -th gate lines G1, G7, etc. is sequentially scanned in the first sub-frame SF1, The second gate group composed of +2 gate lines (G2, G8, etc.) is sequentially scanned in the second sub-frame (SF2). On the same principle, the sixth gate group composed of the (6m + 6) th gate lines (G6, G12, etc.) is sequentially scanned in the sixth sub-frame SF6.

In this manner, the timing controller 11 controls the operation of the gate driver 13 to distribute the n gate groups to n subframes and scan one gate time required for scanning one gate line to n Increase to the horizontal period. Here, the n horizontal period is defined as a value obtained by multiplying one horizontal period defined by dividing one frame period by the number of gate lines by n.

The timing controller 11 generates the switch control signal at the first level LV1 in the first period P1 corresponding to (n-1) / n of the 1-gate time EP as shown in Fig. 6, The switch control signal is generated at the second level LV2 in the second period P2 that is continuous to the first period P1 and corresponds to 1 / n of the one gate time EP. Here, the switch control signal can be any signal as long as it can define n horizontal periods corresponding to the extended one gate time (EP). Preferably, the switch control signal may be selected as a source output enable (SOE) for controlling the output timing of the source driver 12 in accordance with the extended one-gate time (EP) as in Fig. A plurality of gate times (EP) may be included in each subframe.

The source driver 12 includes a shift register, a latch array, a digital-analog converter, an output circuit, and the like. The source driver 12 latches the digital video data RGB according to the source timing control signal and then converts the latched data into an analog positive / negative gamma compensation voltage to convert the data voltages whose polarities are reversed in a predetermined cycle to a plurality of To the data lines 15 through the output channels. The output circuit includes a plurality of buffer portions. The buffer portions are connected to the output channels, and each of the output channels is connected to the data lines 15 on a one-to-one basis. The source driver 12 may reverse the polarity of the data voltages output to the output channels in a column inversion manner to reduce power consumption. On the basis of the column-inversion method, the polarity of the data voltage output from the same output channel is inverted in units of subframes. The polarities of the data voltages output from the neighboring output channels are opposite to each other.

The source driver 12 applies a common voltage Vcom to the data lines 15 during the first period P1 according to the switch control signal of the first level LV1 The common voltage Vcom is supplied to the data lines 15 by shorting the data lines L 1 and L 2 to the data lines L 1 and L 2, (15). The source driver 12 applies the common voltage Vcom to the pixel electrodes of the liquid crystal cells during the first period P1 of each of the gate times EP belonging to each subframe, By making the common voltage Vcom the same, it is possible to prevent accumulation of ion impurities on the surface of the alignment film in the residual DC voltage during low-speed driving.

The gate driver 13 supplies gate pulses to the gate lines 16 in accordance with the gate timing control signals using the shift register and level shifter in the above-described interlace driving method. The shift register of the gate driver 13 may be formed directly on the lower glass substrate according to a gate-driver in panel (GIP) scheme.

FIG. 7 shows switches connected between the output channel of the source driver and the data line for operation as in FIG. FIG. 8 shows a part of the source driver in detail, including the switches of FIG. Fig. 9 shows the switching states of the switches shown in Fig. 8 within one frame. 10 is a waveform diagram for explaining the operations of FIGS. 7 and 8 during the first sub-frame, and FIG. 11 is a waveform diagram for explaining operations of the gates generated in each sub- Pulses, and the data waveforms supplied to the data lines in each of the gate times of each sub-frame.

7, the source driver 12 includes a first output channel CH1 for outputting a first polarity data voltage (positive polarity data voltage) and a second output channel CH2 for outputting a second polarity data voltage (negative polarity data) A first switch group SW1 for switching the current flow between the first output channel CH1 and the second output channel CH2, each output channel CH1 or CH2 and each data line DL1 or DL2, And a second switch group SW2 for switching the current flow between the first switch group DL2 and the second switch group SW2.

As shown in FIG. 8, the first output channel CH1 is connected to a first digital-analog converter (P-DAC) and a first buffer unit BUF1 for buffering the positive gamma compensation voltage. The second output channel (CH2) includes a second digital-analog converter (N-DAC) for converting input digital video data to a negative gamma compensation voltage as shown in FIG. 8, 2 buffer unit BUF2 is connected.

The first buffer unit BUF1 and the second buffer unit BUF2 are supplied with the high potential driving voltage VDD and the ground potential GND and the intermediate potential driving voltage HVDD between these potentials VDD and GND. The voltage level of the intermediate potential driving voltage HVDD corresponds to half of the high potential driving voltage VDD and can be selected to be substantially equal to the common voltage Vcom applied to the liquid crystal display panel 10. [

The first buffer unit BUF1 includes a first input part PI operated by a high potential driving voltage VDD and a ground potential GND and a second input part PI by a high potential driving voltage VDD and an intermediate potential driving voltage HVDD And a first output (PO) to be operated. The second buffer unit BUF2 includes a second input unit NI which is operated by a high potential driving voltage VDD and a ground potential GND and a second input unit NI by a high potential driving voltage VDD and an intermediate potential driving voltage HVDD And a second output (NO) to be operated.

A first dynamic current corresponding to the positive polarity data voltage is output from the first output unit PO or introduced into the first output unit PO by the switching operation of the first output unit PO, The second dynamic current corresponding to the negative data voltage flows out of the second output portion NO or flows into the second output portion NO by the switching operation of the negative output voltage NO. Here, the first and second dynamic currents flow to the data lines through the output channels CH1 and CH2 when implementing a high-gradation image, while the output channels CH1 and CH2 ). ≪ / RTI >

The polarities of the data voltages output from the neighboring output channels CH1 and CH2 are opposite to each other and the polarity of the data voltage output from the same output channel is inverted in units of subframes in the source driver 12, The first switch group SW1 can be configured through the first to fourth polarity inversion switches OS1, OS2, OS3, and OS4.

The first switch group SW1 is switched on the basis of the switch control signal of the second level LV2 to switch the positive polarity data voltage to either the first data line DL1 or the second data line DL2, And selectively supplies the negative data voltage to the other one of the first data line DL1 and the second data line DL2. 9, when n subframes include alternating odd and even subframes, a plurality of gate times are assigned to odd subframes and even subframes, respectively. 9, the ON times of the first and fourth polarity inversion switches OS1 and OS4 are alternated with the ON time of the second and third polarity inversion switches OS2 and OS3 in units of subframes. When the first and fourth polarity inversion switches OS1 and OS4 are turned on in the odd subframe included in one frame, the second and third polarity inversion switches OS2 and OS3 are turned on in the odd subframe included in one frame Can be turned on.

The operation of the first to fourth polarity reversing switches OS1, OS2, OS3 and OS4 constituting the first switch group SW1 will be described in detail with reference to FIG.

The first polarity inversion switch OS1 is turned on only in the second period P2 of each of the gate times EP belonging to each odd subframe to supply the positive polarity data voltage to the first data line DL1 . The fourth polarity inversion switch OS4 is turned on only in the second period P2 of each of the gate times EP belonging to each odd subframe and supplies a negative data voltage to the second data line DL2 . The second polarity inversion switch OS2 is turned on only in the second period P2 of each of the gate times EP belonging to each even subframe to supply the positive polarity data voltage to the second data line DL2 . The third polarity inversion switch OS3 is turned on only in the second period P2 of each of the gate times EP belonging to each even subframe to supply the negative data voltage to the first data line DL1 .

The present invention is characterized in that the number of the first digital-analog converter (P-DAC) and the number of the second digital-analog converter (N-DAC) are different from each other through the alternating operation of the polarity reversing switches OS1, OS2, OS3, The number can be reduced to half each.

The second switch group SW2 is switched in response to the switch control signal of the first level LV1 to short-circuit the first data line DL1 and the second data line DL2 to the common line.

To this end, the second switch group SW2 includes a second-1 equipotential switch SW2-1 connected between the common line and the first data line DL1 as shown in FIG. 8, And a second -2 equipotential switch (SW2-2) connected between the second switch (DL2).

The second -1N equipotential switch SW2-1 is turned on in the first period P1 of each of the gate times EP belonging to each subframe to turn on the first data line DL1 And short-circuits the common line. The 2-2 equipotential switch (SW2-2) turns on simultaneously with the 2-1 equipotential switch (SW2-1) in the first period (P1) of each of the gate times (EP) belonging to each subframe And the second data line DL2 is short-circuited to the common line.

When the first data line DL1 is short-circuited to the common line, the common voltage Vcom is applied to the first data line DL1. Similarly, when the second data line DL2 is short-circuited to the common line, the common voltage Vcom is applied to the second data line DL2. This common voltage Vcom is supplied to the pixel electrodes of the liquid crystal cells connected to the gate lines through the TFTs when the gate pulse is supplied to the corresponding gate lines in each sub-frame. As a result, the pixel electrode and the common electrode of the liquid crystal cells form an equal potential.

For example, as shown in FIGS. 10 and 11, when one frame is time-divided into six sub-frames, the first and seventh gate lines belonging to the first gate group (G Group # 1) Gate pulses are sequentially supplied to the gates G1 and G7. At this time, the one-gate time allocated to scan each of the first and seventh gate lines G1 and G7 is increased to 6H. The first period P1 of each gate time in which the first switch group SW1 is turned off and the second switch group SW2 is turned on is set to the preceding 5H in each gate time, A common voltage is applied to the data lines. On the other hand, the second period P2 of each gate time in which the first switch group SW1 is turned on is set to the remaining 1H in each gate time, and the data voltage is applied to the data lines during the second period P2 .

Figure 12 shows the effect of the present invention in comparison with the prior art.

12, since the data voltage (Vdata) having a polarity is applied to the liquid crystal layer LC of each liquid crystal cell for a long time at the time of low speed driving by the conventional interlace drive, the ion impurities remaining in the liquid crystal cell (PI) surface to change the electrical characteristics and the tilt angle of the liquid crystal LC, resulting in a DC afterimage. Accordingly, in the present invention, only one horizontal period (1H) is supplied for supplying the data voltage (Vdata) during one gate time increased by n horizontal periods (nH) during low-speed driving by interlace driving, The common voltage Vcom is applied to the pixel electrode 1 of the liquid crystal cells. Thus, by making the potentials of the pixel electrode 1 and the common electrode 2 equal to the common voltage Vcom, it is possible to prevent accumulation of ion impurities on the surface of the alignment film PI at a low DC voltage do. 12, 'SUB1' denotes a lower glass substrate, 'SUB2' denotes an upper glass substrate, and 'PAS' denotes an insulating film.

As described above, the present invention increases the one-gate time required to scan one gate line to nH through low-speed driving through the interlace driving technique, Voltage is supplied and a common voltage is supplied to the pixel electrodes of the liquid crystal cells during the remaining (n-1) H of one gate time to form the equal potential between the pixel electrode and the common electrode to prevent accumulation of the residual DC voltage on the surface of the alignment film Thereby minimizing the DC residual image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: Source driver 13: Gate driver
15: Data lines 16: Gate lines

Claims (12)

A display panel in which a plurality of gate lines and a plurality of data lines are crossed and pixels are formed at the intersections;
A gate driver for supplying a gate pulse to the gate lines;
One frame is divided into n sub-frames (n is a positive integer of 2 or more) sub-frames, the gate lines are grouped into n gate groups, and the operation of the gate driver is controlled to control the n gate groups (n-1) / n of the one-gate time, and the gate period is increased to n horizontal periods by scanning one of the gate lines by scattering in n sub- A timing controller generating a control signal at a first level and generating the switch control signal at a second level in a second period that is continuous to the first period and corresponds to 1 / n of the one gate time; And
And a common voltage supply circuit for supplying a common voltage to the data lines by short-circuiting the common lines supplied with the common voltage with the data lines during the first period according to the switch control signal of the first level, And a source driver for supplying a data voltage to the data lines during the second period. The method according to claim 1,
Wherein the n horizontal period is a value obtained by multiplying one horizontal period defined by dividing one frame period by the number of gate lines by n. The method according to claim 1,
Each of the pixels includes:
A pixel electrode to which the data voltage is supplied, a common electrode to which the common voltage is supplied, and a liquid crystal layer formed between the pixel electrode and the common electrode;
Wherein the pixel electrode and the common electrode are at the same potential by a common voltage during the first period. The method according to claim 1,
The source driver,
A first output channel through which a first polarity data voltage is output;
A second output channel through which a second polarity data voltage is output;
Wherein the first polarity data voltage is selectively supplied to one of the first data line and the second data line which are adjacent to each other among the data lines, A first switch group for selectively supplying a polarity data voltage to the other one of the first data line and the second data line; And
And a second switch group which is switched in accordance with the first level switch control signal to short-circuit the first data line and the second data line to the common line. 5. The method of claim 4,
Wherein the subframes include an alternate odd subframe and an even subframe, and a plurality of gate times are allocated to the odd subframe and the even subframe, respectively. 6. The method of claim 5,
The first switch group includes:
A first polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each odd subframe and supplies the first polarity data voltage to the first data line;
A fourth polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each odd subframe and supplies the second polarity data voltage to the second data line;
A second polarity inversion switch that is turned on only in the second period of each of the gate times belonging to each of the even sub-frames to supply the first polarity data voltage to the second data line; And
And a fourth polarity inversion switch which is turned on only in the second period of each of the gate times belonging to each of the even sub-frames to supply the second polarity data voltage to the first data line. Display device. The method according to claim 6,
The second switch group includes:
A second 1 < rd > equalization switch that is turned on in the first period of each of the gate times belonging to each of the subframes to short the first data line to the common line; And
Equipotential switches that simultaneously turn on with the second-equalization switch in the first period of each of the gate times belonging to each of the subframes to short the second data line to the common line Wherein the display device is a display device. The method according to claim 1,
Wherein the switch control signal is selected as a source output enable signal for controlling the output of the source driver. A display panel in which a plurality of gate lines and a plurality of data lines are crossed and pixels are formed at the intersections, a gate driver for supplying gate pulses to the gate lines, and a source driver for driving the data lines. A method of driving a display device,
One frame is divided into n sub-frames (n is a positive integer of 2 or more) sub-frames, the gate lines are grouped into n gate groups, and the operation of the gate driver is controlled to control the n gate groups extending one gate time required for scanning one gate line to n horizontal periods by scattering and scanning in n subframes;
A second period that is continuous to the first period and corresponds to 1 / n of the 1-gate time, in a first period corresponding to (n-1) / n of the 1-gate time, Generating the switch control signal at a second level;
Controlling the operation of the source driver according to the first level switch control signal to supply a common voltage to the data lines by shorting common lines supplied with the common voltage with the data lines during the first period ; And
And controlling the operation of the source driver according to the second level switch control signal to supply the data voltage to the data lines during the second period. 10. The method of claim 9,
Wherein the n horizontal period is a value obtained by multiplying one horizontal period defined as a value obtained by dividing one frame period by the number of gate lines by n. 10. The method of claim 9,
Wherein each of the pixels includes a pixel electrode to which the data voltage is supplied, a common electrode to which the common voltage is supplied, and a liquid crystal layer formed between the pixel electrode and the common electrode;
Wherein the pixel electrode and the common electrode are equipotential by a common voltage during the first period. 10. The method of claim 9,
Wherein the switch control signal is selected as a source output enable signal for controlling the output of the source driver.

Images