KR20060012801A - A driving circuit of a liquid crystal display device and a method for driving the same - Google Patents

Abstract

The present invention relates to a driver of a liquid crystal display device capable of driving data lines in both directions without using a data driver and a method of driving the same. A data driver; And a voltage generator for applying a voltage to the other side of the data lines.

LCD, Data Line, Delay, Pixel Voltage, Data Driver

Description

A driving circuit of a liquid crystal display device and a method for driving the same}

1 is a block diagram of a conventional dual scan type liquid crystal display device

2 is a block diagram of a conventional dual driving type liquid crystal display device

3 is a block diagram of a driving unit of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a circuit diagram of a voltage generator of FIG. 3.

5 is a circuit diagram of a first selector of FIG. 4.

FIG. 6 is a diagram for explaining an effect that a delay of a pixel voltage is compensated by a DC voltage output from a first selector. FIG.

* Explanation of symbols on the main parts of the drawings

311: data driver 322: gate driver

305: gate printed circuit board 301a: first data printed circuit board

301b: second data printed circuit board 371: data drive IC

381: Gate Drive IC 331: Data TCP

341: Gate TCP 390: Dummy TCP

355: voltage generator 300: liquid crystal panel

300a: display area 300b: non-display area

370: FPC (Flexible Printed Circuit) DL: Data Line

GL: Data Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving unit and a driving method thereof for driving a data line in both directions without additionally using a data driver.

In general, a liquid crystal display may be classified into a liquid crystal panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal panel from the outside.

Although not shown in the drawing, the liquid crystal panel is a display device having two transparent substrates (glass substrates) bonded to each other with a predetermined space and a liquid crystal layer formed between the two transparent substrates. One of the two transparent substrates includes a plurality of gate lines arranged at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and the plurality of gate lines. And a pixel electrode formed in each pixel region defined by the data lines, and formed at an intersection of each of the gate lines and the data lines, and switched according to a scan signal of the gate line to switch the pixel voltage from the data line. Is provided with a thin film transistor for transferring each pixel electrode. The other substrate includes a black matrix layer for blocking light in portions other than the pixel region, a color filter layer for implementing color in each pixel region, and an electric field facing the pixel electrode. A common electrode is provided.

On the other hand, as the liquid crystal panel becomes larger, the lengths of the gate lines and the data lines also increase in proportion. As the lengths of the data lines become longer, the resistance and capacitance components of the data lines also increase. Therefore, the longer the data line is, the more delay occurs in the pixel voltage flowing along the data line. In order to prevent the delay of the pixel voltage, a dual scan type liquid crystal display device capable of driving the data line in both directions has been developed.

Hereinafter, a liquid crystal display of a conventional dual scan method will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional dual scan type liquid crystal display device.

As shown in FIG. 1, a conventional dual scan type liquid crystal display device includes a liquid crystal panel 110 defined by a first display area 110a and a second display area 110b, and a liquid crystal panel 110 of the liquid crystal panel 110. A plurality of first gate lines GL1 and first data lines DL1 vertically intersecting with each other formed in the first display area 110a, the first gate lines GL1 and the first data lines. A plurality of thin film transistors (not shown) provided in the pixel region 170a having a matrix form defined by DL1, and a plurality of perpendicular crossings formed in the second display region 110b of the liquid crystal panel 110. A plurality of pixel regions 170b defined by two second gate lines GL2 and second data lines DL2 and the second gate lines GL2 and the second data lines DL2. A plurality of thin film transistors (not shown) and the first gate lines A first gate driver 111a and a first data driver 112a for driving GL1 and the first data lines DL1, the second gate lines GL2 and the second data lines And a second gate driver 111b and a second data driver 112b for driving the DL2. The first and second gate drivers 111a and 111b may include a plurality of gate drive ICs, and the first and second data drivers 112a and 112b may include a plurality of data drive ICs.

On the other hand, although not shown in the drawings, a conventional dual scan type liquid crystal display device includes a timing controller for outputting display data corresponding to the pixel voltage and a first memory and a second for dividing and storing display data output from the timing controller. It further includes a memory. The first memory stores only display data necessary for the first data driver 112a among the display data output from the timing controller, and the second memory stores the second data driver (among the display data output from the timing controller). Only display data necessary for 112b) is stored. Although not shown, each of the data drive ICs includes a shift register array for supplying a sequential source sampling clock (SSC) and the display data in response to the source sampling clock of the shift resist array. First and second latch arrays for latching and outputting the first and second latch arrays, a first multiplexer (hereinafter, referred to as MUX) disposed between the first and second latch arrays, and display data output from the second latch array. A digital-to-analog converter (hereinafter, referred to as a "DAC") array for converting a signal into a pixel voltage, a buffer array for buffering and outputting a pixel voltage output from the DAC array, and a pixel output from the buffer array. And a second MUX array for selecting the path of the voltage. Although not shown in the drawings, each of the data drive ICs included in the first and second data drivers 112a and 112b is mounted in TCP, and the data drive ICs of the first data driver 112a are mounted. TCP is connected between the printed circuit board and one side of the liquid crystal panel 110, and the TCP in which the data drive ICs of the second data driver 112b are mounted is another printed circuit board and the other side of the liquid crystal panel 110. Connected between.

The operation of the conventional dual scan type liquid crystal display device configured as described above will be described in detail.

First, the first gate driver 111a sequentially applies gate driving pulses to the first gate lines GL1, and at the same time, the second gate driver 111b sequentially applies the second gate lines GL2. The gate drive pulse is applied. That is, the first gate lines GL1 and the second gate lines GL2 are simultaneously scanned. As the first gate lines GL1 and the second gate lines GL2 are simultaneously scanned as described above, the first data driver 112a reads display data from the first memory and reads the display data from the first memory. The corresponding pixel voltage is supplied to the first data lines DL1 corresponding to the first gate lines GL1 to which the gate driving pulses are applied. At the same time, the second data driver 112b reads display data from the second memory, and the pixel voltage corresponding to the display data corresponds to the second gate lines GL2 to which the gate driving pulse is applied. Supply to the second data lines DL2. Accordingly, the pixel areas 170a positioned in the first display area 110a and the pixel areas 170b positioned in the second display area 110b simultaneously represent an image.

Meanwhile, a dual driving type liquid crystal display device, which can reduce costs by driving the data lines in both directions without using the first memory and the second memory, has been developed.

2 is a block diagram of a conventional dual driving type liquid crystal display device.

As shown in FIG. 2, a conventional dual driving type liquid crystal display device includes a liquid crystal panel 210 having a plurality of gate lines GL and a plurality of data lines DL perpendicularly intersecting with each other. A plurality of thin film transistors (not shown) provided in the plurality of pixel regions 270 defined in matrix form by the gate lines GL and the data lines DL, and the gate lines GL. ), A gate driver 211 sequentially applying gate driving pulses, a first data driver 212a applying a pixel voltage to one side of the data lines DL, and the other side of the data lines DL. And a second data driver 212b applying the pixel voltage to the pixel voltage. The gate driver 211 may include a plurality of gate drive ICs, and the first and second data drivers 212a and 212b may include a plurality of data drive ICs.

On the other hand, the conventional dual driving method liquid crystal display device further includes a timing controller for outputting a pixel voltage corresponding to the display data. The timing controller provides the same display data to the first and second data drivers 212a and 212b. Although not shown, each of the data drive ICs included in the first and second data drivers 212a and 212b has the same configuration as that of the data drive ICs included in the conventional dual scan type liquid crystal display device. Have Although not shown in the drawings, each of the data drive ICs included in the first and second data drivers 212a and 212b is mounted in TCP, similarly to the conventional dual scan type liquid crystal display device. The TCP in which the data drive IC of the driver 212a is mounted is connected between the printed circuit board and one side of the liquid crystal panel 210, and the TCP in which the data drive ICs of the second data driver 212b are mounted is another print. The circuit board is connected between the other side of the liquid crystal panel 210.

The operation of the conventional dual driving type liquid crystal display device configured as described above will be described in detail.

First, the gate driver 211 sequentially applies gate driving pulses to the gate lines GL. In this case, the first data driver 212a may apply the pixel voltage corresponding to the display data input from the timing controller to one side of the data lines DL corresponding to the gate lines GL to which the gate driving pulse is applied. Is authorized. At the same time, the second data driver 212b provides the pixel voltage corresponding to the display data input from the timing controller to the other side of the data lines DL. That is, the same pixel voltage is simultaneously applied to both sides of the data lines DL, thereby preventing the pixel voltage from being delayed.

However, the conventional dual driving type liquid crystal display device still uses two data drivers (first and second data drivers 212a and 212b). As described above, each of the data drivers 212a and 212b includes a plurality of data drive ICs, and each of the data drive ICs has the configuration described above. As a result, the conventional dual scan and dual drive type liquid crystal display devices have a problem of requiring twice the manufacturing cost compared to a general liquid crystal display device using one data driver.

The present invention has been made to solve the above problems, and includes a data driver for applying a data voltage to one side of the data line and a voltage generator for applying a DC voltage to the other side of the data line in both directions. It is an object of the present invention to provide a driving unit and a driving method thereof for a liquid crystal display device which can reduce manufacturing costs.

The driving unit of the liquid crystal display according to the present invention for achieving the above object includes a data driver for applying a pixel voltage for driving the liquid crystal to one side of the data lines of the liquid crystal panel; And a voltage generator for applying a voltage to the other side of the data lines.

In addition, the driving method of the driving unit of the liquid crystal display according to the present invention configured as described above comprises the steps of: applying a pixel voltage for driving the liquid crystal to one side of the data lines of the liquid crystal panel; And applying a voltage to the other side of the data lines.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a driving unit of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the driving unit of the liquid crystal display according to the exemplary embodiment of the present invention includes a gate driver 322 for supplying gate driving pulses to the gate lines GL of the liquid crystal panel 300, and A data driver 311 for supplying a pixel voltage (analog) to each side of the data lines DL of the liquid crystal panel 300, and a DC voltage having a predetermined level to each other side of the data lines DL. It is configured to include a voltage generator 355.

Here, the gate driver 322 is composed of a plurality of gate drive ICs 381, and the gate drive ICs 381 are each mounted in a gate TCP 341 (Tape Carrier Package). The data driver 311 includes a plurality of data drive ICs 371, and each of the data drive ICs 371 is mounted on the data TCP 331. In addition, a gate printed circuit board 305, a first data printed circuit board 301a, and a second data printed circuit board 301b are disposed around the liquid crystal panel 300, and the gate TCPs 341 are provided. ) Is connected between the gate printed circuit board 305 and the non-display area 300b of the liquid crystal panel 300 to electrically connect the gate printed circuit board 305 and the liquid crystal panel 300. The data TCPs 331 are connected between the first data printed circuit board 301a and the non-display area 300b of the liquid crystal panel 300 to connect the first data printed circuit board 301a to the first data printed circuit board 301a. The liquid crystal panel 300 is electrically connected.

Meanwhile, the second data printed circuit board 301b and the non-display area 300b of the liquid crystal panel 300 are electrically connected by a plurality of dummy TCPs 390. The dummy TCPs 390 may be electrically connected to each other. Each of the data TCPs 331 is provided in one-to-one correspondence. However, the data driver IC 371 is not mounted on the dummy TCPs 390, and only serves to electrically connect the second data printed circuit board 301b and the liquid crystal panel 300. Here, the second data printed circuit board 301 and the liquid crystal panel 300 may be connected using a flexible printed circuit (FPC) instead of the dummy TCP 390. In addition, between each of the printed circuit boards between the gate printed circuit board 305 and the first data printed circuit board 301a and between the gate printed circuit board 305 and the second data printed circuit board 301b. An FPC 370 is provided for electrically connecting the spools.

Here, the gate driver receives control data such as display data (R, G, B) corresponding to the pixel voltage, vertical and horizontal synchronization signals, clock signals, and the like from the interface to the first data printed circuit board (301a). A timing controller (not shown) for formatting and outputting the display data, a clock, and a control signal at a timing suitable for reproducing the screen by the data driver 311 and the liquid crystal panel 300 and the liquid crystal; A power supply unit (not shown) for supplying a voltage required for each part of the display device, and digital data (the display data) input from the data driver 311 by receiving power from the power supply unit, and analog data (the pixel voltage). Gamma reference voltage unit (not shown) for supplying the reference voltage required for conversion to The ryeokdoen DC by using the output voltage of the constant voltage that is used for the liquid crystal panel 300, a gate high voltage, a gate low voltage, the reference voltage and a common voltage, and / DC converting unit (not shown) is mounted. The voltage generator 355 is mounted on the second data printed circuit board 301b.

Although not shown in the drawing, the timing controller receives timing synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, and a clock signal from the interface, and includes the gate driver 322 and the data driver 311. And a control signal generator for generating control signals necessary for the voltage generator 355, and a data signal generator for receiving the display data input from the interface, arranging them, and supplying them to the data driver 311. do. The control signal generator may include a source sampling clock (SSC), a source output enable signal (SOE), and a source start pulse (SSP) based on the input vertical synchronization signal. A polarity reverse signal (POL) is generated and supplied to the data driver 311. The control signal generator generates a gate shift clock (GSC), a gate output enable signal (GOE), a gate start pulse (GSP), and the like based on the vertical synchronization signal input. Is generated and supplied to the gate driver 322 through the gate printed circuit board 305. In addition, the control signal generator generates a load enable signal (LE: Load Enable) based on the vertical synchronization signal input to supply to the voltage generator (355).

On the other hand, the non-described FIG. 300a indicates a display area where an image is displayed.

Here, the voltage generator 355 mounted on the second data printed circuit board 301b will be described in more detail as follows.

4 is a circuit diagram of the voltage generator of FIG. 3.

As shown in FIG. 4, the voltage generator 355 may include a positive voltage power supply 400a that largely outputs a positive DC voltage, a negative voltage power supply 400b that outputs a negative DC voltage, A first selector 450a configured to select one of the positive DC voltage and the negative DC voltage to supply the other of odd-numbered data lines DL of the data lines DL; The second selector 450b selects one of a DC voltage and a negative DC voltage and supplies the second voltage to the other side of the even-numbered data lines DL. In this case, the DC voltage output from the first selector 450a and the DC voltage output from the second selector 450b have inverted polarities.

Specifically, the first selector 450a includes a first NMOS transistor NT1 having a drain, a gate to which the polarity inversion signal POL is applied, and a source to which the positive DC voltage is applied; A first PMOS transistor PT1 having a drain connected to the drain of the first NMOS transistor NT1, a gate to which the polarity inversion signal POL is applied, and a source to which the negative DC voltage is applied; In addition, a source connected in common to the drain of the first NMOS transistor NT1 and the drain of the first PMOS transistor PT1, a gate to which the load enable signal LE is applied, and the odd-numbered data lines DL A second NMOS transistor NT2 having a drain connected to the other side of The second selector 450b includes a second PMOS transistor PT2 having a drain, a gate to which the polarity inversion signal POL is applied, and a source to which the positive DC voltage is applied; A third NMOS transistor NT3 having a drain connected to the drain of the second PMOS transistor PT2, a gate to which the polarity inversion signal POL is applied, and a source to which the negative DC voltage is applied; In addition, a source connected to the drain of the second PMOS transistor PT2 and the drain of the third NMOS transistor NT3 in common, a gate receiving the load enable signal LE, and the even-numbered data lines And a fourth NMOS transistor NT4 having a drain connected to the other side of the DL.

The operation of the driver of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail as follows.

First, display data and control signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal are input from an external system (not shown) to the interface. Thereafter, the interface formats the display data, the horizontal synchronizing signal, the vertical synchronizing signal, and the clock signal into a low voltage differential signal (LVDS) method or a transistor transistor logic (TTL) method to provide the timing controller. In this case, the data signal generator of the timing controller may include a source sampling clock (SSC), a source output enable signal (SOE), a source start pulse (SSP), a polarity inversion signal (POL), and a gate shift based on the vertical synchronization signal. A clock GSC, a gate output enable signal GOE, a gate start pulse GSP, a load enable signal LE, and the like, and generate the source sampling clock SSC, the source output enable signal SOE, A source start pulse SSP and a polarity inversion signal POL are supplied to the data driver 311, and the gate shift clock (GSC), a gate output enable signal (GOE), and a gate start pulse (GSP) are provided. ) Is supplied to the gate driver 322 through the gate printed circuit board 305. The timing controller supplies the load enable signal LE to the voltage generator 355. The data signal generator of the timing controller rearranges the display data and supplies the data to the data driver 311.

Thereafter, the gate driver 322 sequentially supplies the gate high voltage to the gate lines GL in response to the control signals GSP, GSC, and GOE from the timing controller. Accordingly, the gate driver 322 causes the thin film transistors connected to the gate lines GL to be driven in units of the gate lines GL. In detail, the gate driver 322 generates the shift pulse by shifting the gate start pulse GSP according to the gate shift pulse GSC. The gate driver 322 supplies the gate high voltage to the corresponding gate line GL every horizontal time 1H in response to the shift pulse. In this case, the gate driver 322 outputs the gate high voltage only during the period corresponding to the enable period of the gate output enable signal GOE. The gate driver 322 supplies the gate low voltage in the remaining periods when the gate high voltage is not supplied to the gate lines GL.

On the other hand, the data driver 311 applies a pixel voltage of one horizontal line to each one side of the data lines DL every 1H in response to control signals SSP, SSC, SOE, and POL from a timing controller. Supply. In particular, the data driver 311 converts display data, which is a digital signal input from the timing controller, into a pixel voltage, which is an analog signal, using a gamma voltage from a gamma voltage generator (not shown). Supply to each side of (DL). In detail, the data driver 311 generates a sampling signal by shifting the source start pulse SSP according to the source shift clock SSC. Subsequently, the data driver 311 sequentially receives and latches the display data R, G, and B in predetermined units in response to the sampling signal. The data driver 311 simultaneously latches the latched display data R, G, and B for the horizontal line at the rising edge of the source output enable signal SOE, and latches the latched display data. Simultaneously outputs the polling edge of the source output enable signal SOE. In this case, the output display data is converted into a pixel voltage by the gamma reference voltage unit and simultaneously supplied to one side of the data lines DL. The data driver 311 supplies the pixel voltage to each side of the data lines for a period corresponding to an enable period of the source output enable signal SOE. The data driver 311 inverts the polarities of pixel voltages applied to the odd-numbered data lines DL and the even-numbered data lines DL in response to the polarity control signal POL. . The polarity control signal POL is a signal whose polarity is inverted in the 1H period.

For example, when the polarity control signal POL is high logic, the data driver 311 popularizes a positive pixel voltage in the odd-numbered data lines DL, and the even-numbered data lines DL. ), A negative pixel voltage is applied. On the other hand, when the polarity control signal POL is low logic, each data driver 311 applies a negative pixel voltage to the odd-numbered data lines DL and the even-numbered data lines DL. ), A positive pixel voltage is applied. By inverting the polarity of the pixel voltage in this way, the liquid crystal panel 300 is driven in a dot inversion method.

In the present invention, for convenience of description, a positive pixel voltage is applied to the odd-numbered data lines DL and a negative pixel voltage is applied to the even-numbered data lines DL. Meanwhile, the polarity control signal POL is applied to the voltage generator 355 through the second data printed circuit board 301b, and in response to the polarity control signal POL of the voltage generator 355. The first selector 450a outputs a positive DC voltage, and the output positive DC voltages are applied to the other sides of the odd-numbered data lines DL through the dummy TCP 390, respectively. In addition, in response to the polarity control signal POL, the second selector 450b of the voltage generator 355 outputs a negative DC voltage, and the output DC DC voltage is the dummy TCP ( 390 is applied to the other sides of the even-numbered data lines DL, respectively. If this is explained in more detail as follows.

First, the polarity control signal POL is the gate of the first NMOS transistor NT1 of the first selector 450a, the gate of the first PMOS transistor PT1 of the first selector 450a, and the first. It is input to the gate of the second PMOS transistor PT2 of the second selector 450b and the gate of the third NMOS transistor NT3 of the second selector 450b. Here, when the polarity inversion signal POL has a high logic for the first 1H, the first NMOS transistor NT1 and the third NMOS transistor NT3 are turned on and the first PMOS transistor PT1 is turned on. ) And the second PMOS transistor PT2 are turned off. Accordingly, the positive DC voltage is charged to the source of the second NMOS transistor NT2 via the turned-on first NMOS transistor NT1. The negative DC voltage is charged to the source of the fourth NMOS transistor NT3 via the turned-on third NMOS transistor NT3.

Subsequently, the load enable signal LE output from the timing controller is applied to the gate of the second NMOS transistor NT2 and the gate of the fourth NMOS transistor NT4, so that the second NMOS transistor NT2 and The fourth NMOS transistor NT4 is turned on. Then, the positive DC voltage charged to the source of the second NMOS transistor NT2 is input to the other side of the odd-numbered data lines DL via the turned-on second NMOS transistor NT2. In addition, the negative DC voltage charged to the source of the fourth NMOS transistor NT4 is input to the other sides of the even-numbered data lines DL via the turned-on fourth NMOS transistor NT4. The load enable signal LE is a signal synchronized with the source output enable signal SOE, and the second NMOS transistor NT2 and the fourth NMOS transistor NT4 are the load enable signal (S). LE is turned on in the high logic period (corresponding to the disable period of the source output enable signal SOE). In other words, the second NMOS transistor NT2 and the fourth NMOS transistor NT4 correspond to an enable period of the source output enable signal SOE (a period in which the pixel voltage is applied to the data line DL). Is turned on in the high logic section of the load enable signal LE. Therefore, the positive DC voltage and the negative DC voltage switched by the second NMOS transistor NT2 and the fourth NMOS transistor NT4 are on the other side of the data lines DL at a time earlier than the pixel voltage. Supplied.

In summary, a positive pixel voltage is supplied to one side of odd-numbered data lines DL of the data lines DL during a first 1H period, and a positive polarity is supplied to other sides of the odd-numbered data lines DL. DC voltage is supplied. In addition, a negative pixel voltage is supplied to one side of even-numbered data lines DL of the data lines DL during the first 1H period, and a negative side of the other-numbered data lines DL is supplied to one side of the even-numbered data lines DL. Polarity DC voltage is supplied.

Meanwhile, a negative pixel voltage is supplied to one side of the odd-numbered data lines DL during the second 1H period, and a negative DC voltage is supplied to the other side of the odd-numbered data lines DL, respectively. . In addition, a positive pixel voltage is supplied to one side of the even-numbered data lines DL during the second 1H period, and a positive DC voltage is supplied to the other side of the even-numbered data lines DL.

As described above, when the pixel voltage and the DC voltage are simultaneously applied to each of the data lines DL, how the delay of the pixel voltage is prevented will be described in detail. For convenience of explanation, the pixel voltage and the DC voltage applied to any one odd-numbered data line will be described.

FIG. 5 is a circuit diagram of the first selector of FIG. 4, and FIG. 6 is a diagram for describing an effect that a delay of a pixel voltage is compensated by a DC voltage output from the first selector.

First, the positive pixel voltage and the positive DC voltage applied to the data line DL during the first 1H period H1 will be described.

As shown in FIG. 6, both the polarity control signal POL and the load enable signal LE have high logic during the first period T1 of the first 1H period H1, and the first period T1. The source output enable signal SOE has a disable period. Accordingly, in response to the high logic polarity control signal POL, the data driver 371 selects a positive pixel voltage (+ Vd), and according to the high logic polarity control signal POL, the first NMOS transistor ( NT1 is turned on to charge the positive DC voltage (+ Vdc) to the source of the second NMOS transistor NT2, and the second NMOS transistor NT2 is connected to the high logic load enable signal LE. It is turned on by supplying a positive DC voltage (+ Vdc) is charged to the source to the other side of the data line (DL). In this case, the positive DC voltage (+ Vdc) is supplied to the other side of the data line DL for a period corresponding to the high logic period of the load enable signal LE.

Thereafter, the polarity control signal POL maintains high logic for the second period T2, and the load enable signal LE has low logic. The source output enable signal SOE has an enable period. Here, the second period T2 corresponds to an enable period of the source output enable signal SOE. Accordingly, in response to the source output enable signal SOE, the data driver 371 applies the positive pixel voltage + Vd for a period corresponding to the enable period of the source output enable signal SOE. It is supplied to one side of the data line DL. In this case, since the positive pixel voltage (+ Vd) is pre-charged by the positive DC voltage (+ Vdc) previously applied to the data line (DL), the resistance of the data line (DL) ( Delay of the positive pixel voltage (+ Vd) due to the R) component and the capacitance component (C) can be prevented, so that the positive pixel voltage (+ Vd) is the in of the source output enable signal SOE. The desired target voltage value (+ Vo) is maintained for the period corresponding to the enable period.

Next, the negative pixel voltage (-Vd) and the positive DC voltage (+ Vdc) applied to the data line DL during the second 1H period H2 will be described.

As shown in FIG. 5, both the polarity control signal POL and the load enable signal LE have a low logic during the third period T3, and the source output enable signal during the third period T3. SOE) has a disable period. Accordingly, in response to the low logic polarity control signal POL, the data driver 371 selects a negative pixel voltage (-Vd), and the first PMOS is driven by the low logic polarity control signal POL. The transistor PT1 is turned on to charge the negative DC voltage -Vdc to the source of the second NMOS transistor NT2, and the second NMOS transistor NT2 is connected to the high logic load enable signal LE is turned on to supply the negative DC voltage (-Vdc) charged to the source to the other side of the data line DL. In this case, the negative DC voltage -Vdc is supplied to the other side of the data line DL for a period corresponding to a high logic period of the load enable signal LE.

Thereafter, the polarity control signal POL maintains low logic for the fourth period T4, and the load enable signal LE has low logic. The source output enable signal SOE has an enable period. The fourth period T4 corresponds to an enable period of the source output enable signal SOE. Accordingly, in response to the source output enable signal SOE, the data driver 371 may apply the negative pixel voltage -Vd for a period corresponding to the enable period of the source output enable signal SOE. It is supplied to one side of the data line DL. Accordingly, since the negative pixel voltage (-Vd) is precharged by the negative DC voltage (-Vdc) previously applied to the data line DL, the resistance R of the data line DL is applied. Delay of the negative pixel voltage (-Vd) due to the capacitance component (C) and the capacitance component (C), and the negative pixel voltage (-Vd) of the source output enable signal (SOE) The desired target voltage value (-Vo) is maintained for a period corresponding to the enable period.

On the other hand, since the DC voltage is a voltage having a constant magnitude regardless of the gradation of the pixel voltage, it is necessary to have the most optimized voltage magnitude for the pixel voltage of all gradations. That is, when the positive DC voltage (+ Vdc) has the same voltage magnitude as that of the maximum voltage among the pixel voltages, that is, the pixel voltage of the highest grayscale (black) in the normally white mode, all grayscales corresponding to the positive polarity The delay of the pixel voltage can be compensated most effectively, and the negative DC voltage (-Vdc) is equal to the minimum voltage among the pixel voltages, that is, the voltage magnitude of the pixel voltage of the lowest gray scale (white) in the normally white mode. When having a magnitude, the delay of the pixel voltage of all gray levels corresponding to the negative polarity can be most effectively compensated for. Substantially, the positive DC voltage (+ Vdc) preferably has a voltage magnitude of about 0.2V lower than the pixel voltage of the highest gray level, and the negative DC voltage (-Vdc) is about the pixel voltage of the lowest gray level. It is desirable to have a voltage magnitude as high as 0.2V.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving unit and the driving method thereof according to the present invention have the following effects.

The pixel voltage and the DC voltage for preventing the delay of the pixel voltage are applied to the data line of the driving unit of the liquid crystal display according to the present invention. Here, the pixel voltage is supplied from a data driver, and the DC voltage is supplied from a voltage generator. The voltage generator is a simple circuit for supplying only positive and negative DC voltages, and may be configured at a lower cost than data drive ICs included in the data driver.

That is, since the driving unit of the liquid crystal display device of the present invention does not use two data drivers as in the related art, and uses one data driver and the voltage generator, the data line can be driven in both directions at a lower cost than before.

Claims (14)

A data driver for applying a pixel voltage for driving the liquid crystal to one side of the data lines of the liquid crystal panel; And And a voltage generator for applying a voltage to the other side of the data lines. The method of claim 1, And the voltage is applied to the data lines before the pixel voltage. The method of claim 2, And the voltage is a direct current voltage. The method of claim 1, The voltage generator includes a positive voltage power supply for outputting a positive DC voltage; A negative voltage power supply for outputting a negative DC voltage; A first selector configured to select one of the positive DC voltage and the negative DC voltage to supply the other of odd-numbered data lines of the data lines; And And a second selector configured to select one of the positive DC voltage and the negative DC voltage to supply the other of the even-numbered data lines of the data lines. The method of claim 4, wherein And wherein the positive DC voltage has the same voltage level as the pixel voltage of the highest gradation. The method of claim 4, wherein And the DC voltage of the negative polarity has the same voltage as the pixel voltage of the lowest gray level. The method of claim 4, wherein And a direct current voltage output from the first selector and a direct current voltage output from the second selector have inverted polarities. The method of claim 4, wherein The first selector may include a first NMOS transistor having a drain, a gate to which a polarity inversion signal is applied, and a source to which the positive DC voltage is applied; A PMOS transistor having a drain connected to the drain of the first NMOS transistor, a gate to which the polarity inversion signal is applied, and a source to which the negative DC voltage is applied; And And a second NMOS transistor having a drain connected to the drain of the first NMOS transistor and a drain of the PMOS transistor, a gate to which an enable signal is applied, and a drain connected to the other sides of the odd-numbered data lines. Driver of liquid crystal display device. The method of claim 4, wherein The second selector may include a PMOS transistor having a drain, a gate to which the polarity inversion signal is applied, and a source to which the positive DC voltage is applied; A first NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate to which the polarity inversion signal is applied, and a source to which the negative DC voltage is applied; And a second NMOS transistor having a drain connected to the drain of the PMOS transistor and a drain of the first NMOS transistor, a gate to which the enable signal is applied, and a drain connected to the other sides of the even-numbered data lines. The driving unit of the liquid crystal display device. The method of claim 1, And a TCP for electrically connecting the printed circuit board on which the voltage generator is mounted and the printed circuit board and the data lines. The method of claim 10, And a driving unit connecting the printed circuit board and the data lines with an FPC. Applying a pixel voltage for driving a liquid crystal to one side of data lines of the liquid crystal panel; And And applying a voltage to the other side of the data lines. The method of claim 12, And the voltage is applied to the data lines before the pixel voltage. The method of claim 13, And the voltage is a direct current voltage.

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